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1. 发明授权

US07349399B1 Method and apparatus for out-of-order processing of packets using linked lists 有权
标题翻译：使用链表对数据包进行无序处理的方法和装置
公开(公告)号：US07349399B1
公开(公告)日：2008-03-25
申请号：US10327555
申请日：2002-12-20
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

2. 发明授权

US07808999B2 Method and apparatus for out-of-order processing of packets using linked lists 有权
标题翻译：使用链表对数据包进行无序处理的方法和装置
公开(公告)号：US07808999B2
公开(公告)日：2010-10-05
申请号：US12054235
申请日：2008-03-24
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

3. 发明申请

US20080259928A1 Method and Apparatus for Out-of-Order Processing of Packets using Linked Lists 有权
标题翻译：使用链接列表对包进行无序处理的方法和装置
公开(公告)号：US20080259928A1
公开(公告)日：2008-10-23
申请号：US12054235
申请日：2008-03-24
申请人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
发明人： Edmund G. Chen , John G. Favor , Ruchi Wadhawan , Gregory G. Minshall
IPC分类号： H04L12/56
CPC分类号： H04L49/9094 , H04L49/90
摘要： These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes storing information regarding each of the packets in a shared reorder buffer. The method also includes for each of the plurality of reorder contexts, maintaining a reorder context linked list that records the order in which those of the packets that were designated for that reorder context and that are currently stored in the shared reorder buffer were received relative to the global order. The method also includes completing processing of at least certain of the packets out of the global order and retiring the packets from the shared reorder buffer out of the global order for at least certain of the packets.
摘要翻译：将参照具体实施方式和附图更好地描述本发明的这些和其它方面。描述了使用链表对包进行无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括将关于每个分组的信息存储在共享重排序缓冲器中。该方法还包括对于多个重排序上下文中的每一个，维护重排序上下文链接列表，其记录其中针对该重排序上下文指定的分组以及当前存储在共享重排序缓冲器中的分组的顺序相对于全球秩序。该方法还包括完成处于全局顺序中的至少某些分组的处理，并且至少在某些分组中从全局顺序退出来自共享重排序缓冲器的分组。

4. 发明授权

US07512129B1 Method and apparatus for implementing a switching unit including a bypass path 有权
标题翻译：用于实现包括旁路路径的切换单元的方法和装置
公开(公告)号：US07512129B1
公开(公告)日：2009-03-31
申请号：US10299236
申请日：2002-11-18
申请人： John G. Favor , Edmund G. Chen , Ruchi Wadhawan
发明人： John G. Favor , Edmund G. Chen , Ruchi Wadhawan
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： H04L49/9094 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9047
摘要： A method and apparatus for processing out-of-order processing of packets is described. In one embodiment, the method includes receiving a packet, which is in an original position relative to other packets; and attempting, by a primary processing unit, to classify and process the packet. The method also includes determining whether the packet was completely classified and processed by the primary processing unit; and upon determining that the primary processing unit completely classified and processed the packet, bypassing a secondary processing unit. The method also includes transmitting the packet onto a network, the packet being transmitted in its original position relative to the other packets.
摘要翻译：描述了用于处理分组的无序处理的方法和装置。在一个实施例中，该方法包括接收相对于其他分组处于原始位置的分组; 并且由主处理单元尝试对分组进行分类和处理。该方法还包括确定分组是否被主处理单元完全分类和处理; 并且一旦确定所述主处理单元完全对所述分组进行了分类和处理，则绕过所述辅助处理单元。该方法还包括将分组发送到网络上，该分组相对于其他分组在其原始位置被发送。

5. 发明授权

US07349398B1 Method and apparatus for out-of-order processing of packets 有权
标题翻译：分组无序处理的方法和装置
公开(公告)号：US07349398B1
公开(公告)日：2008-03-25
申请号：US10193504
申请日：2002-07-10
申请人： John G. Favor , Edmund G. Chen , Stephan Meier
发明人： John G. Favor , Edmund G. Chen , Stephan Meier
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.
摘要翻译：描述了用于分组的无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。该方法还包括基于序列号从共享重排序缓冲器中重新分组，所述序列号相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排除。

6. 发明授权

US07852846B2 Method and apparatus for out-of-order processing of packets 有权
标题翻译：分组无序处理的方法和装置
公开(公告)号：US07852846B2
公开(公告)日：2010-12-14
申请号：US12054236
申请日：2008-03-24
申请人： John G. Favor , Edmund G. Chen , Stephan Meier
发明人： John G. Favor , Edmund G. Chen , Stephan Meier
IPC分类号： H04L12/56 , H04L12/54 , G06F9/44
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.
摘要翻译：描述了用于分组的无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。该方法还包括基于序列号从共享重排序缓冲器中重新分组，所述序列号相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排除。

7. 发明申请

US20080259960A1 Method and apparatus for Out-of-Order Processing of Packets 有权
标题翻译：分组无序处理的方法和装置
公开(公告)号：US20080259960A1
公开(公告)日：2008-10-23
申请号：US12054236
申请日：2008-03-24
申请人： John G. Favor , Edmund G. Chen , Stephan Meier
发明人： John G. Favor , Edmund G. Chen , Stephan Meier
IPC分类号： H04L29/04
CPC分类号： H04L49/9094 , H04L49/90
摘要： A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for each of the plurality of reorder contexts, assigning reorder context sequence numbers indicating an order relative to the global order of the packets designated for that reorder context. The method also includes storing packet descriptors for each of the packets in a shared reorder buffer, and completing processing of at least certain of the packets out of the global order. The method also includes, for each of the plurality of reorder contexts, maintaining a first indication of the one of the sequence numbers assigned the one of the packets that is next to be retired for that reorder context. The method also includes retiring the packets from the shared reorder buffer, based on the sequence numbers, in order with respect to each of the plurality of reorder contexts, but out of the global order for at least certain of the packets.
摘要翻译：描述了用于分组的无序处理的方法和装置。在一个实施例中，所述方法包括以全局顺序接收分组，所述分组被指定用于多个重排序上下文中的不同的分组。该方法还包括对于多个重排序上下文中的每一个，分配指示相对于针对该重排序上下文指定的分组的全局顺序的顺序的重排序上下文序列号。该方法还包括将分组描述符存储在共享重排序缓冲器中的每个分组，以及完成来自全局顺序的至少某些分组的处理。对于多个重排序上下文中的每一个，该方法还包括为该重排序上下文保留下一个待退休的分组之一的序列号之一的第一指示。该方法还包括基于序列号从共享重排序缓冲器中退出分组，以相对于多个重排序上下文中的每一个依次排列，但是对于至少某些分组的全局顺序排列。

8. 发明授权

US06237083B1 Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence 失效
标题翻译：微处理器包括映射到同一逻辑存储器的多个寄存器文件，并且响应于在指令序列中包含指令而禁止寄存器文件之间的同步
公开(公告)号：US06237083B1
公开(公告)日：2001-05-22
申请号：US09110518
申请日：1998-07-06
申请人： John G. Favor
发明人： John G. Favor
IPC分类号： G06F9312
CPC分类号： G06F9/30181 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/3885
摘要： A microprocessor includes a first register file including a plurality of multimedia registers defined to store operands for multimedia instructions and a second register file including a plurality of floating point registers defined to store operands for floating point instructions. The multimedia registers and floating point registers are mapped to the same logical storage according to the instruction set employed by the microprocessor. In order to maintain predefined behavior when a floating point instruction reads a register most recently updated by a multimedia instruction or vice versa, the microprocessor provides for synchronization of the first and second register files between executing a set of one or more multimedia instructions and a set of one or more floating point instructions (where either set may be prior to the other in program order and the order affects which direction copying of the contents is performed, i.e. first register file to second register file or vice versa). The predefined behavior in the above mentioned circumstances is thereby maintained. The microprocessor supports an empty state instruction. If the empty state instruction is included between the set of one or more multimedia instructions and the set of one or more floating point instructions in a code sequence, the microprocessor inhibits the register file synchronization. In one embodiment including the x86 instruction set, the empty state instruction performs the same set of actions as the EMMS instruction in addition to the above mentioned features.
摘要翻译：微处理器包括第一寄存器文件，其包括被定义为存储用于多媒体指令的操作数的多个多媒体寄存器，以及包括多个浮点寄存器的第二寄存器堆，所述多个浮点寄存器被定义为存储用于浮点指令的操作数。多媒体寄存器和浮点寄存器根据微处理器采用的指令集映射到相同的逻辑存储器。为了在浮点指令读取由多媒体指令最近更新的寄存器或反之亦然时保持预定义的行为，微处理器在执行一组一个或多个多媒体指令和一组之间提供第一和第二寄存器文件的同步一个或多个浮点指令（其中任一集合可以在程序顺序中彼此之前），并且该顺序影响执行内容的复制方式，即首先将文件注册到第二寄存器文件，反之亦然）。从而保持上述情况下的预定义的行为。微处理器支持空状态指令。如果在一个或多个多媒体指令的集合和代码序列中的一个或多个浮点指令的集合之间包括空状态指令，则微处理器禁止寄存器文件同步。在包括x86指令集的一个实施例中，空状态指令除了上述特征之外还执行与EMMS指令相同的一组动作。

9. 发明授权

US6061521A Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle 失效
标题翻译：具有多媒体操作的计算机在单个指令周期内可执行为两组不同的操作
公开(公告)号：US6061521A
公开(公告)日：2000-05-09
申请号：US759042
申请日：1996-12-02
申请人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Gary W. Thome , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3824
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions. A first logic portion may be coupled to receive a first operand from a fixed slot of a first register and a second operand from any slot of a second register. A second logic portion may be coupled to receive a third operand from a fixed slot of the first register and a fourth operand from any slot of the second register. The first logic portion may perform an arithmetic operation dissimilar from the second logic portion.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地路由和组合在矢量ALU。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。在一个实施例中，算术逻辑单元可以被划分为至少两个逻辑部分。第一逻辑部分可以被耦合以从第二寄存器的任何时隙的第一寄存器的固定时隙和第二操作数接收第一操作数。第二逻辑部分可以被耦合以从第一寄存器的固定时隙接收第三操作数，并从第二寄存器的任何时隙接收第四操作数。第一逻辑部分可以执行与第二逻辑部分不同的算术运算。

10. 发明授权

US06047372A Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot 有权
标题翻译：用于从固定寄存器时隙将一个操作数路由到算术逻辑单元的装置，以及来自任何寄存器时隙的另一个操作数的装置
公开(公告)号：US06047372A
公开(公告)日：2000-04-04
申请号：US290837
申请日：1999-04-13
申请人： John S. Thayer , Brian E. Longhenry , John G. Favor , Frederick D. Weber
发明人： John S. Thayer , Brian E. Longhenry , John G. Favor , Frederick D. Weber
IPC分类号： G06F9/30 , G06F9/302 , G06F9/312 , G06F9/315 , G06F7/00
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3877
摘要： A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment multiple ALUs may each receive one operand from a fixed source register slot location, where the fixed slot location may be different for each ALU. The operand routing may provide another operand from any source register slot location for another input to each respective ALU.
摘要翻译：提供多媒体扩展单元（MEU）用于执行各种多媒体类型操作。 MEU可以通过协处理器总线或本地CPU总线耦合到常规处理器。 MEU使用向量寄存器，向量ALU和操作数路由单元（ORU）来尽可能少地执行多媒体操作。通过根据期望的算法流程图将操作数布置在向量ALU上来容易地执行复杂算法。 ORU使用MAU特有的向量指令对齐向量寄存器的分区插槽或子时隙内的操作数。在ORU的输出端，矢量源或目标寄存器的操作数对可以很容易地在矢量ALU中路由和组合。向量指令采用特殊的加载/存储指令与许多操作指令相结合，对对齐的操作数执行并发的多媒体操作。在一个实施例中，多个ALU可以从固定的源寄存器时隙位置接收一个操作数，其中固定的时隙位置对于每个ALU可以是不同的。操作数路由可以从任何源寄存器时隙位置提供另一个操作数，用于另一个输入到每个相应的ALU。

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