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1. 发明申请

US20100153893A1 CONSTRAINT MANAGEMENT AND VALIDATION FOR TEMPLATE-BASED CIRCUIT DESIGN 有权
标题翻译：基于模式的电路设计的约束管理和验证
公开(公告)号：US20100153893A1
公开(公告)日：2010-06-17
申请号：US12333050
申请日：2008-12-11
申请人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
发明人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译：公开了一种用于基于模板的设备设计的约束管理和验证的技术。该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。模板级表示包括一个或多个模板层次结构。每个模板表示电子设备设计的相应部分。该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。

2. 发明授权

US06539470B1 Instruction decode unit producing instruction operand information in the order in which the operands are identified, and systems including same 有权
标题翻译：指令解码单元按照操作数被识别的顺序产生指令操作数信息，以及包括其的系统
公开(公告)号：US06539470B1
公开(公告)日：2003-03-25
申请号：US09441632
申请日：1999-11-16
申请人： Eric W. Mahurin , Brian D. McMinn
发明人： Eric W. Mahurin , Brian D. McMinn
IPC分类号： G06F930
CPC分类号： G06F9/30167 , G06F9/30152 , G06F9/3816 , G06F9/382
摘要： An instruction decode unit is described including circuitry coupled to receive an instruction. The instruction identifies multiple operands, one of which is a destination operand. The circuitry responds to the instruction by producing: (i) operand codes specifying the operands, wherein the operand codes are produced in the order in which the operands are identified within the instruction, and (ii) a destination operand signal identifying the destination operand. In one embodiment, the decode unit responds to the instruction by producing the operand codes, operand address information, control signals, and the destination operand signal. A processor including the instruction decode unit is also described, as is a computer system including the processor. The instruction may include operand information which identifies the operands. The instruction may also include destination operand information which indicates which of the operands is the destination operand. The circuitry may produce the destination operand signal dependent upon the destination operand information. The instruction may be a member of an instruction set including instructions having a variable number of bytes. In one particular example, the instruction may be an x86 instruction including operand information which identifies two operands. The instruction may include a direction bit, and the value of the direction bit may indicate which of the two operands is the destination operand. In this case, the circuitry may produce the destination operand signal dependent upon the value of the direction bit.
摘要翻译：描述了指令解码单元，其包括耦合以接收指令的电路。该指令标识多个操作数，其中一个是目标操作数。电路通过产生以下命令来响应该指令：（i）指定操作数的操作数代码，其中操作数代码以指令内的操作数被识别的顺序产生，以及（ii）标识目的地操作数的目的地操作数信号。在一个实施例中，解码单元通过产生操作数代码，操作数地址信息，控制信号和目的地操作数信号来响应该指令。还描述了包括指令解码单元的处理器，以及包括处理器的计算机系统。指令可以包括标识操作数的操作数信息。指令还可以包括指示哪个操作数是目的地操作数的目的地操作数信息。电路可以根据目的地操作数信息产生目的地操作数信号。指令可以是包括具有可变字节数的指令的指令集的成员。在一个特定示例中，该指令可以是包括标识两个操作数的操作数信息的x86指令。指令可以包括方向位，并且方向位的值可以指示两个操作数中的哪一个是目的地操作数。在这种情况下，电路可以根据方向位的值产生目标操作数信号。

3. 发明授权

US5926646A Context-dependent memory-mapped registers for transparent expansion of a register file 失效
标题翻译：上下文相关的内存映射寄存器，用于透明扩展寄存器文件
公开(公告)号：US5926646A
公开(公告)日：1999-07-20
申请号：US927337
申请日：1997-09-11
申请人： James K. Pickett , Rupaka Mahalingaiah , Brian D. McMinn
发明人： James K. Pickett , Rupaka Mahalingaiah , Brian D. McMinn
IPC分类号： G06F9/30 , G06F9/318 , G06F9/46 , G06F9/32 , G06F12/06
CPC分类号： G06F9/30138 , G06F9/30112 , G06F9/30123 , G06F9/30185 , G06F9/463
摘要： A microprocessor includes an expanded set of registers in addition to the architected set of registers specified by the microprocessor architecture employed by the microprocessor. The expanded set of registers are memory-mapped within the context of the program being executed. Upon a context switch, the microprocessor saves the state of the expanded registers to the corresponding memory locations. An application program may make use of the expanded registers by assigning the most-often used operands in the program to the set of memory locations corresponding to the expanded registers. The application programmer may than code instructions which access these operands with register identifiers corresponding to the expanded registers. In one embodiment, the microprocessor implements a portion of the expanded registers instead of the entire set of expanded registers. The implemented portion of the expanded registers are accessed as register accesses, while the unimplemented portion are converted to memory accesses. The decode unit within the microprocessor may be configured to convert instructions which are coded to access the unimplemented expanded registers into memory operations to access the corresponding memory location.
摘要翻译：微处理器除了由微处理器采用的微处理器结构指定的结构化寄存器组之外还包括一组扩展寄存器。扩展的寄存器组在正在执行的程序的上下文中进行存储器映射。在上下文切换时，微处理器将扩展的寄存器的状态保存到相应的存储器位置。应用程序可以通过将程序中最经常使用的操作数分配给对应于扩展寄存器的存储器单元组来利用扩展寄存器。应用程序员可以编码使用与扩展寄存器对应的寄存器标识符来访问这些操作数的指令。在一个实施例中，微处理器实现扩展寄存器的一部分，而不是整个扩展寄存器组。扩展寄存器的实现部分作为寄存器访问进行访问，而未实现的部分被转换为存储器访问。微处理器内的解码单元可以被配置为将编码的指令转换成存取操作，以访问未实现的扩展寄存器以访问对应的存储单元。

4. 发明授权

US5430394A Configuration and method for testing a delay chain within a microprocessor clock generator 失效
标题翻译：用于测试微处理器时钟发生器内的延迟链的配置和方法
公开(公告)号：US5430394A
公开(公告)日：1995-07-04
申请号：US212037
申请日：1994-03-11
申请人： Brian D. McMinn , Stephen C. Horne
发明人： Brian D. McMinn , Stephen C. Horne
IPC分类号： G01R31/28 , G01R31/30 , G06F1/04 , G06F1/06 , G06F11/22 , G06F15/78 , H03K3/02 , H03K5/13 , H03H11/26 , H03J1/04
CPC分类号： H03K5/131 , G01R31/30 , H03K5/133
摘要： A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time. If no manufacturing defects are present, the four outputs of the variable delay units should be virtually indistinguishable from one another. The results of the compare operation may be driven on external pins of the microprocessor or may be processed internally within the microprocessor. Similar tests may be conducted throughout the entire operating range of the variable delay units.
摘要翻译：提供了一种测试配置，其允许将微处理器时钟发生器的延迟链内的多个可变延迟单元相对于彼此进行比较。在正常操作期间，插入在延迟链内的一组多路复用器被配置为使得多个可变延迟单元相对于彼此串联电耦合。可以向微处理器提供外部命令信号以启动测试操作，其中可变延迟单元被测试可能的缺陷。在测试操作期间，控制单元选择多路复用器使得四个延迟单元彼此电分离。然后，通过两个或多个可变延迟单元同时驱动公共测试信号，并且耦合到每个可变延迟单元的输出的比较电路确定通过每个可变延迟单元传播的公共脉冲信号中的转变是否基本相同时间。如果不存在制造缺陷，则可变延迟单元的四个输出应该几乎不能彼此区分。比较操作的结果可以在微处理器的外部引脚上驱动，或者可以在微处理器内部进行处理。类似的测试可以在可变延迟单元的整个操作范围内进行。

5. 发明授权

US4731737A High speed intelligent distributed control memory system 失效
标题翻译：高速智能分布式控制存储系统
公开(公告)号：US4731737A
公开(公告)日：1988-03-15
申请号：US860608
申请日：1986-05-07
申请人： David B. Witt , Brian D. McMinn
发明人： David B. Witt , Brian D. McMinn
IPC分类号： G06F15/16 , G06F7/24 , G06F12/00 , G06F13/16 , G06F15/17 , G06F17/30 , G06F7/00
CPC分类号： G06F17/30952 , G06F17/30982 , G06F7/24
摘要： A highspeed, intelligent, distributed control memory system is comprised of an array of modular, cascadable, integrated circuit devices, hereinafter referred to as "memory elements." Each memory element is further comprised of storage means, programmable on board processing ("distributed control") means and means for interfacing with both the host system and the other memory elements in the array utilizing a single shared bus. Each memory element of the array is capable of transferring (reading or writing) data between adjacent memory elements once per clock cycle. In addition, each memory element is capable of broadcasting data to all memory elements of the array once per clock cycle. This ability to asynchronously transfer data between the memory elements at the clock rate, using the distributed control, facilitates unburdening host system hardware and software from tasks more efficiently performed by the distributed control. As a result, the memory itself can, for example, perform such tasks as sorting and searching, even across memory element boundaries, in a manner which conserves, is faster and more efficient then using, host system resources.
摘要翻译：高速，智能的分布式控制存储器系统由一系列模块化，可级联的集成电路器件组成，以下称为“存储元件”。每个存储元件还包括存储装置，可编程板载处理（“分布式控制”）装置和用于使用单个共享总线与主机系统和阵列中的其它存储器元件两者进行接口的装置。阵列的每个存储元件能够在每个时钟周期之间传送（读取或写入）相邻存储器元件之间的数据。此外，每个存储元件能够每时钟周期向阵列的所有存储元件广播数据一次。这种使用分布式控制以时钟速率在存储器元件之间异步传输数据的能力有助于从分布式控制更有效地执行的任务中减轻主机系统硬件和软件的负担。因此，内存本身例如可以以保存的方式，甚至跨存储器元素边界执行诸如排序和搜索之类的任务，因此使用主机系统资源更快，更有效率。

6. 发明授权

US07127573B1 Memory controller providing multiple power modes for accessing memory devices by reordering memory transactions 有权
标题翻译：存储器控制器通过重新排序存储器事务来提供用于访问存储器件的多种功率模式
公开(公告)号：US07127573B1
公开(公告)日：2006-10-24
申请号：US09564765
申请日：2000-05-04
申请人： Geoffrey S. S. Strongin , Brian D. McMinn , Dale E. Gulick
发明人： Geoffrey S. S. Strongin , Brian D. McMinn , Dale E. Gulick
IPC分类号： G06F12/06
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0215 , G06F13/1626 , G06F13/1694 , Y02D10/13 , Y02D10/14
摘要： A memory controller includes a power mode sensitive reordering device coupled to receive a power mode indication. The memory controller includes a selectable high and low power mode. An indication of which of the high and low power modes is selected is coupled to the power mode sensitive reordering device as the power mode indication. In the low power mode, memory transactions are reordered to minimize power consumption in memory devices controlled by the memory controller.
摘要翻译：存储器控制器包括耦合以接收功率模式指示的功率模式敏感重新排序装置。存储器控制器包括可选择的高和低功率模式。选择高功率模式和低功率模式中的哪一种的指示作为功率模式指示耦合到功率模式敏感重新排序装置。在低功耗模式下，存储器事务被重新排序以最小化由存储器控制器控制的存储器件中的功耗。

7. 发明授权

US07080170B1 Circular buffer using age vectors 失效
标题翻译：使用年龄向量的循环缓冲
公开(公告)号：US07080170B1
公开(公告)日：2006-07-18
申请号：US10653750
申请日：2003-09-03
申请人： Gerald D. Zuraski, Jr. , Brian D. McMinn , Michael K. Ciraula
发明人： Gerald D. Zuraski, Jr. , Brian D. McMinn , Michael K. Ciraula
IPC分类号： G06F3/00 , G06F9/30
CPC分类号： G06F9/3842 , G06F5/10 , G06F9/3855
摘要： An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.
摘要翻译：一种装置包括缓冲器，该缓冲器包括多个条目，多个老化向量以及耦合到该缓冲器的控制电路。每个年龄向量对应于一个或多个条目。响应于提供给要写入至少第一条目的缓冲器的数据，控制电路被配置为产生第一时代向量。第一年龄向量对应于第一条目，并且指示多个条目中的哪个条目包含比被写入第一条目的数据更早的数据。控制电路被配置为响应于多个年龄向量来选择用于读取的条目。所选择的条目具有用于选择所选条目的属性，并且在对应于所选条目的年龄向量中指示为存储较旧数据的其他条目不具有该属性。

8. 发明授权

US06760392B1 Method and apparatus to provide fixed latency early response in a system with multiple clock domains with fixable clock ratios 失效
标题翻译：在具有可固定时钟比的多个时钟域的系统中提供固定延迟早期响应的方法和装置
公开(公告)号：US06760392B1
公开(公告)日：2004-07-06
申请号：US09439191
申请日：1999-11-12
申请人： Teik-Chung Tan , Brian D. McMinn
发明人： Teik-Chung Tan , Brian D. McMinn
IPC分类号： H04L700
CPC分类号： H04L7/0331 , H04L7/02
摘要： A system and method for transferring data using an early response signal to indicate subsequent transmission of data after a fixed latency, wherein the signal and data are transferred from a first clock domain to a second clock domain using a clock skipping technique. In one embodiment, an early response signal is transmitted by a first device k clock pulses prior to transmission of the data. The receiving device, which is operating at a higher clock rate, receives the early response signal and delays the signal by the number of skipped pulses which will occur in the second clock domain before the occurrence of the kth valid pulse. The second device employs a skip pattern generator to generate a signal indicative of this number of skipped pulses and provides the number to a delay circuit which delays the early response signal for an this number of clock pulses. The delayed early response signal is then output to the appropriate logic to indicate the latency of the subsequent data transfer.
摘要翻译：一种用于使用早期响应信号传送数据以指示固定等待时间之后的数据传输的系统和方法，其中使用时钟跳过技术将信号和数据从第一时钟域传送到第二时钟域。在一个实施例中，早期响应信号在传输数据之前由第一设备k个时钟脉冲发送。以较高时钟速率工作的接收设备接收早期响应信号，并且在第k个有效脉冲发生之前将信号延迟将在第二时钟域中发生的跳过脉冲数。第二设备使用跳过模式发生器来产生指示该跳跃脉冲数的信号，并将数量提供给延迟电路，该延迟电路延迟这个数量的时钟脉冲的早期响应信号。然后将延迟的早期响应信号输出到适当的逻辑以指示随后的数据传送的等待时间。

9. 发明授权

US6151662A Data transaction typing for improved caching and prefetching characteristics 失效
标题翻译：用于改进缓存和预取特征的数据事务输入
公开(公告)号：US6151662A
公开(公告)日：2000-11-21
申请号：US982720
申请日：1997-12-02
申请人： David S. Christie , Brian D. McMinn , Stephan G. Meier , James K. Pickett
发明人： David S. Christie , Brian D. McMinn , Stephan G. Meier , James K. Pickett
IPC分类号： G06F9/318 , G06F9/38 , G06F12/08 , G06F12/12
CPC分类号： G06F9/30192 , G06F12/0862 , G06F12/0888 , G06F9/30047 , G06F9/345 , G06F9/383 , G06F2212/6028
摘要： A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.
摘要翻译：微处理器为每个指令分配数据事务类型。数据交易类型基于指令的编码，并且指示对应于指令的存储器操作的访问模式。访问模式可以例如指定用于存储器操作的缓存和预取特性。选择每个数据事务类型的访问模式以增强微处理器对数据的访问速度，或通过禁止对这些存储器操作的高速缓存和/或预取来增强微处理器的总体缓存和预取效率。不依赖数据存储器访问模式和整体程序行为来确定高速缓存和预取操作，而是依据逐个指令来确定这些操作。此外，分配给不同指令编码的数据事务类型可能会显示给程序开发人员。程序开发人员可以使用指令编码（以及分配给导致默认访问模式的零数据事务类型的指令编码）来优化程序执行期间处理器资源的使用。

10. 发明授权

US6138213A Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line 失效
标题翻译：缓存包括用于存储预取高速缓存行的预取方式，并且被配置为在访问预取的高速缓存行时将预取的高速缓存行移动到非预取方式
公开(公告)号：US6138213A
公开(公告)日：2000-10-24
申请号：US884434
申请日：1997-06-27
申请人： Brian D. McMinn
发明人： Brian D. McMinn
IPC分类号： G06F12/08 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/0864 , G06F2212/6022
摘要： A cache employs one or more prefetch ways for storing prefetch cache lines and one or more ways for storing accessed cache lines. Prefetch cache lines are stored into the prefetch way, while cache lines fetched in response to cache misses for requests initiated by a microprocessor connected to the cache are stored into the non-prefetch ways. Accessed cache lines are thereby maintained within the cache separately from prefetch cache lines. When a prefetch cache line is presented to the cache for storage, the prefetch cache line may displace another prefetch cache line but does not displace an accessed cache line. A cache hit in either the prefetch way or the non-prefetch ways causes the cache line to be delivered to the requesting microprocessor in a cache hit fashion. The cache is further configured to move prefetch cache lines from the prefetch way to the non-prefetch way if the prefetch cache lines are requested (i.e. they become accessed cache lines). Instruction cache lines may be moved immediately upon access, while data cache line accesses may be counted and a number of accesses greater than a predetermined threshold value may occur prior to moving the data cache line from the prefetch way to the non-prefetch way. Additionally, movement of an accessed cache line from the prefetch way to the non-prefetch way may be delayed until the accessed cache line is to be replaced by a prefetch cache line.
摘要翻译：高速缓存采用一种或多种预取方法来存储预取高速缓存行和一种或多种用于存储所访问的高速缓存行的方式。预取缓存行被存储在预取方式中，而响应于连接到高速缓存的微处理器启动的请求的高速缓存未命中而获取的高速缓存行被存储到非预取方式中。因此，访问的高速缓存行与预取高速缓存行分开地保持在高速缓存内。当将预取高速缓存行呈现给高速缓存用于存储时，预取高速缓存行可以替换另一个预取高速缓存行，但不会移位所访问的高速缓存行。以预取方式或非预取方式的缓存命中导致高速缓存行以缓存命中方式传送到请求的微处理器。如果预取高速缓存行被请求（即，它们变为被访问的高速缓存行），则高速缓存进一步被配置为将预取高速缓存行从预取方式移动到非预取方式。可以在访问时立即移动指令高速缓存行，同时可以对数据高速缓存行访问进行计数，并且在将数据高速缓存行从预取方式移动到非预取方式之前可能会发生大于预定阈值的访问次数。此外，访问的高速缓存行从预取方式移动到非预取方式可能被延迟，直到所访问的高速缓存行被替换为预取高速缓存行。

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