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1. 发明授权

US06873184B1 Circular buffer using grouping for find first function 有权
标题翻译：循环缓冲器使用分组查找第一个功能
公开(公告)号：US06873184B1
公开(公告)日：2005-03-29
申请号：US10653802
申请日：2003-09-03
申请人： Brian D. McMinn , Michael K. Ciraula , Gerald D. Zuraski, Jr.
发明人： Brian D. McMinn , Michael K. Ciraula , Gerald D. Zuraski, Jr.
IPC分类号： G06F5/10 , G06F12/00 , G06F12/08
CPC分类号： G06F5/10 , G06F12/0862 , G06F2205/106
摘要： An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.
摘要翻译：一种装置包括缓冲器，该缓冲器包括多个条目，插入指针，删除指针，耦合到缓冲器的多个第一控制电路以及耦合到缓冲器的第二控制电路。这些条目在逻辑上分为多个组。每个第一控制电路对应于相应的组，并从相应组中选择一个来自缓冲器的电位读取的条目。此外，在删除指针指示相应组中的第一条目并且插入指针围绕缓冲器包围并指示相应组中的第二条目的情况下，每个第一控制电路选择第一条目，如果第一条目有资格选择。第二控制电路选择第一组，并且由第一控制电路从第一组中选择的条目是从缓冲器读取的条目。

2. 发明授权

US07080170B1 Circular buffer using age vectors 失效
标题翻译：使用年龄向量的循环缓冲
公开(公告)号：US07080170B1
公开(公告)日：2006-07-18
申请号：US10653750
申请日：2003-09-03
申请人： Gerald D. Zuraski, Jr. , Brian D. McMinn , Michael K. Ciraula
发明人： Gerald D. Zuraski, Jr. , Brian D. McMinn , Michael K. Ciraula
IPC分类号： G06F3/00 , G06F9/30
CPC分类号： G06F9/3842 , G06F5/10 , G06F9/3855
摘要： An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.
摘要翻译：一种装置包括缓冲器，该缓冲器包括多个条目，多个老化向量以及耦合到该缓冲器的控制电路。每个年龄向量对应于一个或多个条目。响应于提供给要写入至少第一条目的缓冲器的数据，控制电路被配置为产生第一时代向量。第一年龄向量对应于第一条目，并且指示多个条目中的哪个条目包含比被写入第一条目的数据更早的数据。控制电路被配置为响应于多个年龄向量来选择用于读取的条目。所选择的条目具有用于选择所选条目的属性，并且在对应于所选条目的年龄向量中指示为存储较旧数据的其他条目不具有该属性。

3. 发明授权

US5566130A Address transition detection (ATD) circuit for asynchronous VLSI chips 失效
标题翻译：用于异步VLSI芯片的地址转换检测（ATD）电路
公开(公告)号：US5566130A
公开(公告)日：1996-10-15
申请号：US555601
申请日：1995-11-09
申请人： Christopher M. Durham , Michael K. Ciraula , Craig L. Stephen
发明人： Christopher M. Durham , Michael K. Ciraula , Craig L. Stephen
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18
摘要： A logic filtered address transition detection circuit that receives a chip select signal and an ATD pulse, and which produces an internal clock pulse using:an AND gate, a filtered input terminal, a delay unit and a comparator unit. The AND gate outputs an AND logic signal after processing the chip select signal and ATD pulse, the filtered input terminal and delay unit both receive the AND logic signal from the AND gate; and send their signals to the comparator unit. The comparator unit performs a logic function on the AND logic signal and a delayed AND logic signal to produce the internal clock signal.
摘要翻译：一种逻辑滤波地址转换检测电路，其接收片选信号和ATD脉冲，并且使用与门，滤波后的输入端，延迟单元和比较器单元产生内部时钟脉冲。 AND门在处理芯片选择信号和ATD脉冲后输出一个AND逻辑信号，滤波后的输入端和延时单元都从AND门接收AND逻辑信号; 并将其信号发送到比较器单元。比较器单元在AND逻辑信号和延迟的AND逻辑信号上执行逻辑功能以产生内部时钟信号。

4. 发明授权

US07355881B1 Memory array with global bitline domino read/write scheme 有权
标题翻译：具有全局位线多米诺骨牌读/写方案的内存阵列
公开(公告)号：US07355881B1
公开(公告)日：2008-04-08
申请号：US11285670
申请日：2005-11-22
申请人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
发明人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
IPC分类号： G11C11/00 , G11C7/10 , G11C7/00
CPC分类号： G11C7/18 , G11C7/1051 , G11C7/1057 , G11C7/12 , G11C2207/002
摘要： A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.
摘要翻译：使用全局位线多米诺读/写方案实现存储器阵列的电路。存储器电路包括多个单元，每个单元被配置为存储一位数据。存储器电路还包括多个本地位线，其中每个单元耦合到本地位线之一。多个本地位线中的每一个是具有由一对晶体管交叉耦合的信号路径和互补信号路径的差分位线。

5. 发明授权

US5615168A Method and apparatus for synchronized pipeline data access of a memory system 失效
标题翻译：用于存储器系统的同步流水线数据访问的方法和装置
公开(公告)号：US5615168A
公开(公告)日：1997-03-25
申请号：US538085
申请日：1995-10-02
申请人： George M. Lattimore , Michael K. Ciraula , Manoj Kumar , Joseph M. Poplawski, Jr. , Dieter F. Wendel , Friedrich Wernicke
发明人： George M. Lattimore , Michael K. Ciraula , Manoj Kumar , Joseph M. Poplawski, Jr. , Dieter F. Wendel , Friedrich Wernicke
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1072
摘要： A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.
摘要翻译：用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。存储器系统还包括地址解码器和感测使能电路。地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。

6. 发明授权

US5301165A Chip select speedup circuit for a memory 失效
标题翻译：用于存储器的片选加速电路
公开(公告)号：US5301165A
公开(公告)日：1994-04-05
申请号：US967366
申请日：1992-10-28
申请人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
发明人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
IPC分类号： G11C11/41 , G11C8/18 , G11C7/00
CPC分类号： G11C8/18
摘要： A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to select mode, there appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such a false transition as an actual transition, local clock pulse generators are used which only detect high to low transitions in the chip select mode.
摘要翻译：提供了具有选择和取消选择模式的存储器电路。存储电路作为其用于快速访问数据的技术的一部分，包括响应于检测到地址转换而产生脉冲的电路。当存储器电路从取消选择模式切换到选择模式时，即使没有地址转换，也会出现地址转换。为了防止与解释这样的虚拟转换相关联的延迟作为实际转换，使用本地时钟脉冲发生器，其仅检测芯片选择模式中的高到低转换。

7. 发明授权

US5146111A Glitch-proof powered-down on chip receiver with non-overlapping outputs 失效
标题翻译：具有不重叠输出的芯片接收器的毛刺阻断掉电
公开(公告)号：US5146111A
公开(公告)日：1992-09-08
申请号：US683236
申请日：1991-04-10
申请人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
发明人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
IPC分类号： H03K3/356 , H03K5/1252
CPC分类号： H03K3/356113 , H03K5/1252
摘要： A circuit for providing a glitch-proof, powered-down inactive state to a memory array is disclosed. Cross-coupled NAND gates provide non-overlapping true/complement outputs for an on-chip receiver. Stable inactivation of both true and complement outputs is ensured without performance degrading delay stages.
摘要翻译：公开了一种用于向存储器阵列提供防毛刺，断电无动作状态的电路。交叉耦合NAND门为片上接收器提供非重叠的真/补输出。确保真实和补码输出的稳定失效，而无需降级延迟阶段。

8. 发明授权

US4996670A Zero standby power, radiation hardened, memory redundancy circuit 失效
标题翻译：零备用电源，辐射硬化，存储器冗余电路
公开(公告)号：US4996670A
公开(公告)日：1991-02-26
申请号：US414889
申请日：1989-09-28
申请人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
发明人： Michael K. Ciraula , Christopher M. Durham , Derwin L. Jallice
IPC分类号： G11C5/00 , G11C17/16 , G11C29/00 , G11C29/04
CPC分类号： G11C29/785 , G11C17/16 , G11C29/83 , G11C5/005
摘要： A fused, redundancy selection circuit is disclosed which is disabled by the absence of a chip select signal. The circuit has the feature of avoiding the use of nodes with a floating potential and in this manner it provides an enhanced radiation hardened characteristic. The circuit is effectively disabled if no redundancy is required on a particular memory chip, by leaving fuses which are a part of the circuit, intact. Alternately, if the memory chip is tested to have defects, the redundancy circuit is selectively enabled to provide the desired redundancy for the chip, by blowing fuses which are a part of the circuit. Thereafter, the redundancy circuit is now an active part of the memory chip and it is selectively enabled when the chip select signal is applied to the chip. An advantageous feature of the circuit is that it does not dissipate power when its function is not required either because its enabling fuses have not been blown or alternately when the chip select signal is off. In this manner, a zero standby power, radiation hardened memory redundancy circuit has been provided.

9. 发明授权

US07417449B1 Wafer stage storage structure speed testing 失效
标题翻译：晶圆级存储结构速度测试
公开(公告)号：US07417449B1
公开(公告)日：2008-08-26
申请号：US11274595
申请日：2005-11-15
申请人： Randal L. Posey , Michael K. Ciraula
发明人： Randal L. Posey , Michael K. Ciraula
IPC分类号： G01R31/02
CPC分类号： G01R31/318511 , G01R31/31917
摘要： A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.
摘要翻译：一种用于在半导体晶片上测试集成电路存储结构的系统。在半导体晶片上制造的测试IC包括例如随机存取存储器结构的测试存储结构和包括一个或多个时钟源的访问控制器。在各种实施例中，时钟源可以包括环形振荡器和脉冲宽度发生器。这些时钟源可以是可编程的，以提供具有用于访问存储结构的各种频率的时钟信号。在一个实施例中，由访问控制器提供的频率可以高于可以从ATE提供给晶片的频率。在另一个实施例中，脉冲宽度发生器可以是可编程的，以提供具有各种占空比的脉冲串。

10. 发明授权

US07268591B1 Decode structure with parallel rotation 有权
标题翻译：并行旋转解码结构
公开(公告)号：US07268591B1
公开(公告)日：2007-09-11
申请号：US11274876
申请日：2005-11-15
申请人： Jan-Michael Huber , Michael K. Ciraula
发明人： Jan-Michael Huber , Michael K. Ciraula
IPC分类号： G11C8/00 , G06F12/00
CPC分类号： G11C8/10
摘要： A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.
摘要翻译：存储器子系统及其操作方法。存储器子系统包括具有2个N个位置的存储器阵列。存储器子系统包括地址解码器和旋转逻辑，每个逻辑单元被耦合以接收具有n个地址位的第一地址的位。如果第一地址落在指定的地址范围内，旋转逻辑还被耦合以接收指示第一地址将被移位的位置数量的m个旋转位。旋转逻辑和地址解码器被配置为彼此并行操作。地址选择逻辑被耦合以从地址解码器接收第一多个输出和来自旋转逻辑的第二多个输出，并且还被配置为基于第一和第二多个输出来选择第二地址。

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