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1. 发明授权

US08010920B2 Constraint management and validation for template-based circuit design 有权
标题翻译：基于模板的电路设计的约束管理和验证
公开(公告)号：US08010920B2
公开(公告)日：2011-08-30
申请号：US12333050
申请日：2008-12-11
申请人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
发明人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译：公开了一种用于基于模板的设备设计的约束管理和验证的技术。该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。模板级表示包括一个或多个模板层次结构。每个模板表示电子设备设计的相应部分。该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。

2. 发明申请

US20100153893A1 CONSTRAINT MANAGEMENT AND VALIDATION FOR TEMPLATE-BASED CIRCUIT DESIGN 有权
标题翻译：基于模式的电路设计的约束管理和验证
公开(公告)号：US20100153893A1
公开(公告)日：2010-06-17
申请号：US12333050
申请日：2008-12-11
申请人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
发明人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译：公开了一种用于基于模板的设备设计的约束管理和验证的技术。该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。模板级表示包括一个或多个模板层次结构。每个模板表示电子设备设计的相应部分。该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。

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