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1. 发明申请

US20100153893A1 CONSTRAINT MANAGEMENT AND VALIDATION FOR TEMPLATE-BASED CIRCUIT DESIGN 有权
标题翻译：基于模式的电路设计的约束管理和验证
公开(公告)号：US20100153893A1
公开(公告)日：2010-06-17
申请号：US12333050
申请日：2008-12-11
申请人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
发明人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译：公开了一种用于基于模板的设备设计的约束管理和验证的技术。该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。模板级表示包括一个或多个模板层次结构。每个模板表示电子设备设计的相应部分。该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。

2. 发明授权

US08010920B2 Constraint management and validation for template-based circuit design 有权
标题翻译：基于模板的电路设计的约束管理和验证
公开(公告)号：US08010920B2
公开(公告)日：2011-08-30
申请号：US12333050
申请日：2008-12-11
申请人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
发明人： Richard L. Bartolotti , Thomas D. Burd , Brian D. McMinn , William A. McGee , Arun Chandra
IPC分类号： G06F9/455
CPC分类号： G06F17/505
摘要： A technique for constraint management and validation for template-based device designs is disclosed. The technique includes generating a template-level representation of an electronic device design based on a transistor-level representation of the electronic device design. The template-level representation includes one or more hierarchies of templates. Each template represents a corresponding portion of the electronic device design. The technique further includes determining constraint declarations associated with the electronic device design and verifying whether there is a functional equivalence between the template-level representation to a register-transfer-level (RTL) representation of the electronic device design. The technique additionally includes verifying whether the constraint declarations are valid and verifying the electronic device design responsive to verifying the functional equivalence and verifying the constraint declarations.
摘要翻译：公开了一种用于基于模板的设备设计的约束管理和验证的技术。该技术包括基于电子设备设计的晶体管级表示来生成电子设备设计的模板级表示。模板级表示包括一个或多个模板层次结构。每个模板表示电子设备设计的相应部分。该技术还包括确定与电子设备设计相关联的约束声明，以及验证模板级表示与电子设备设计的寄存器传送级（RTL）表示之间是否具有功能等同性。该技术另外包括验证约束声明是否有效并且响应于验证功能等同性并验证约束声明来验证电子设备设计。

3. 发明授权

US06798712B2 Wordline latching in semiconductor memories 失效
标题翻译：半导体存储器中的字线锁定
公开(公告)号：US06798712B2
公开(公告)日：2004-09-28
申请号：US10190372
申请日：2002-07-02
申请人： Bruce Alan Gieseke , William A. McGee , Ognjen Milic-Strkalj
发明人： Bruce Alan Gieseke , William A. McGee , Ognjen Milic-Strkalj
IPC分类号： G11C800
CPC分类号： G11C8/16 , G11C8/06
摘要： A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.
摘要翻译：提供了一种存储器系统及其操作方法，其具有用于存储数据的存储单元，用于将数据写入并从存储器单元读取数据的位线，以及连接到存储器单元的字线，用于使位线将数据写入存储器单元响应于字线信号。解码器连接到字线，用于响应于时钟信号和地址信号接收和解码地址信息，以选择用于写入存储器单元的字线。锁存电路连接到解码器和字线。锁存电路响应于时钟信号，用于将字线信号提供给所选择的字线以用于对存储器单元的写入，并且当对存储器单元的写入完成时从所选择的字线中去除字线信号。

4. 发明授权

US6078487A Electro-static discharge protection device having a modulated control input terminal 失效
标题翻译：具有调制控制输入端子的静电放电保护装置
公开(公告)号：US6078487A
公开(公告)日：2000-06-20
申请号：US853840
申请日：1997-05-09
申请人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
发明人： Hamid Partovi , Kaizad R. Mistry , David B. Krakauer , William A. McGee
IPC分类号： H03K17/0814 , H02H9/00
CPC分类号： H01L27/0266 , H03K17/08142
摘要： A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.
摘要翻译：保护集成电路（IC）器件免受静电放电（ESD）损坏的电路。保护电路包括N沟道金属氧化物半导体场效应晶体管（MOSFET）钳位装置和栅极调制电路。 MOSFET钳位的源极和漏极连接在IC的输入/输出（I / O）焊盘和接地参考电压之间。在IC的正常工作期间，栅极调制电路通过将其栅极端子连接到接地参考电压来禁用MOSFET钳位。这允许信号电压在I / O焊盘和连接到焊盘的任何操作电路之间通过。在ESD事件期间，栅极调制电路将栅极连接到I / O焊盘，这使得MOSFET钳位能够使任何ESD电压和所产生的电流通过MOSFET钳位分流到地。因此，ESD钳位通过MOSFET沟道电流的增加而不是通过结击穿而达到其钳位到快速恢复电压。这确保了ESD钳位在工作电路结点击穿开始之前达到其回跳电压。该电路在集成电路中特别有用，其中标准ESD钳位晶体管的栅极氧化物太薄，无法保护操作逻辑免受大于操作逻辑电路所用电源电压的I / O信号电压的影响。

5. 发明授权

US08347250B2 Method and apparatus for addressing and improving holds in logic networks 有权
标题翻译：用于寻址和改进逻辑网络中的保持的方法和装置
公开(公告)号：US08347250B2
公开(公告)日：2013-01-01
申请号：US12975668
申请日：2010-12-22
申请人： George A. Gonzalez , Pete J. Hannan , William A. McGee , Vasant Palisetti , Ashok Venkatachar
发明人： George A. Gonzalez , Pete J. Hannan , William A. McGee , Vasant Palisetti , Ashok Venkatachar
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504 , G06F2217/84
摘要： A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
摘要翻译：一种用于修改同步逻辑网络的方法和装置，使得在所有引脚处计算出的保持松弛大于或等于用户指定的阈值，条件是任何引脚上的建立松弛不会变得负或小于用户指定保证金结果是改进的设计，由于保持时间违规而不太可能失败。该方法和装置引入了有限数量的逻辑单元，其有助于将功耗和设计尺寸保持在最小。

6. 发明授权

US06760855B1 System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay 有权
标题翻译：通过选择性地延迟具有不同的多个预定延迟量的地址和数据线来减少写入期间的接地反弹的系统和方法
公开(公告)号：US06760855B1
公开(公告)日：2004-07-06
申请号：US09594833
申请日：2000-06-14
申请人： William A. McGee , Philip Enrique Madrid
发明人： William A. McGee , Philip Enrique Madrid
IPC分类号： G06F118
CPC分类号： G06F13/4217 , G06F13/4072 , H03K5/133 , H03K2005/00156 , H03K2005/00234
摘要： The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.
摘要翻译：本发明涉及一种用于在从微处理器写入操作期间减少接地反弹的方法和相关结构。更具体地说，微处理器的地址和数据信号线被分成三个传输组。第一传输组将其数据无延迟地转换到总线上。第二传输组以核心频率时钟的半个时钟周期延迟将其信号线转换到总线上。最后，第三个传输组以核心频率时钟的全时钟周期延迟将其信号线转换到总线上。以这种方式，微处理器的并行写入使其电流吸收与在核心频率时钟的整个时钟周期分布的写入相关联，使得与该电流吸收相关联的接地反弹减小。

7. 发明申请

US20120167030A1 METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS 有权
标题翻译：用于寻址和改进逻辑网络中的HOLDS的方法和装置
公开(公告)号：US20120167030A1
公开(公告)日：2012-06-28
申请号：US12975668
申请日：2010-12-22
申请人： George A. Gonzalez , Pete J. Hannan , William A. McGee , Vasant Palisetti , Ashok Venkatachar
发明人： George A. Gonzalez , Pete J. Hannan , William A. McGee , Vasant Palisetti , Ashok Venkatachar
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/504 , G06F2217/84
摘要： A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.
摘要翻译：一种用于修改同步逻辑网络的方法和装置，使得在所有引脚处计算出的保持松弛大于或等于用户指定的阈值，条件是任何引脚上的建立松弛不会变得负或小于用户指定保证金结果是改进的设计，由于保持时间违规而不太可能失败。该方法和装置引入了有限数量的逻辑单元，其有助于将功耗和设计尺寸保持在最小。

8. 发明授权

US06807107B1 Semiconductor memory with shadow memory cell 失效
标题翻译：具有阴影存储单元的半导体存储器
公开(公告)号：US06807107B1
公开(公告)日：2004-10-19
申请号：US10190396
申请日：2002-07-02
申请人： William A. McGee , Ognjen Milic-Strkalj , Bruce Alan Gieseke
发明人： William A. McGee , Ognjen Milic-Strkalj , Bruce Alan Gieseke
IPC分类号： G11C1604
CPC分类号： G11C11/412 , G11C7/22 , G11C2207/2245 , G11C2211/4013
摘要： A memory system having a memory cell subject to read and write operations with shadow circuitry including a shadow cell configured to parallel operation of the memory cell. A wordline is connected to the memory cell and bitlines are connected to the memory cell and the shadow cell. Sense circuitry is connected to the bitlines for receiving data from the memory cell. An interlock cell is connected to the sense circuitry and the shadow cell to determine an occurrence of a non-redundant write operation, to provide the non-redundant write operation to the shadow cell, and to have the shadow cell prepare the bitlines for a read operation upon completion of the non-redundant write operation.
摘要翻译：具有存储单元的存储器系统，所述存储单元经受具有阴影电路的读和写操作，所述阴影电路包括配置成并行所述存储单元的影子单元。字线连接到存储单元，位线连接到存储单元和阴影单元。感测电路连接到位线，用于从存储器单元接收数据。互锁单元连接到感测电路和阴影单元以确定非冗余写入操作的发生，以向阴影单元提供非冗余写操作，并使阴影单元准备读取位线完成非冗余写入操作时的操作。

9. 发明授权

US06363471B1 Mechanism for handling 16-bit addressing in a processor 有权
标题翻译：在处理器中处理16位寻址的机制
公开(公告)号：US06363471B1
公开(公告)日：2002-03-26
申请号：US09476323
申请日：2000-01-03
申请人： Stephan G. Meier , Bruce A. Gieseke , William A. McGee , Ramsey W. Haddad
发明人： Stephan G. Meier , Bruce A. Gieseke , William A. McGee , Ramsey W. Haddad
IPC分类号： G06F1200
CPC分类号： G06F9/3855 , G06F9/30036 , G06F9/355 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3859 , G06F12/1036
摘要： A processor includes an address generation unit (AGU) which adds address operands and the segment base. The AGU may add the segment base and the displacement while other address operands are being read from the register file. The sum of the segment base and the displacement may subsequently be added to the remaining address operands. The AGU receives the addressing mode of the instruction, and if the addressing mode is 16 bit, the AGU zeros the carry from the sixteenth bit to the seventeenth bit of the sums generated therein. Additionally, in parallel, the AGU determines if a carry from the sixteenth bit to the seventeenth bit would occur if the logical address were added to the segment base. In one embodiment, the sum of the address operands and the segment base, with carries from the sixteenth bit to the seventeenth bit zeroed, and the carry generated in parallel are provided to a translation lookaside buffer (TLB), which stores translations in the same format (sum and carry). In another embodiment, the AGU corrects the most significant bits of the generated sum based on the carry. The AGU and/or TLB may provide reduced address generation latency while handling the 16 bit addressing mode as defined in the instruction set architecture.
摘要翻译：处理器包括地址生成单元（AGU），其添加地址操作数和段基。 AGU可以在从寄存器文件读取其他地址操作数的同时添加段基址和位移。可以随后将段基数和位移的和添加到剩余的地址操作数。 AGU接收指令的寻址模式，如果寻址模式为16位，则AGU将从第16位到第17位的进位置零。另外，并行地，AGU确定如果将逻辑地址添加到段基础，是否将发生从第16位到第17位的进位。在一个实施例中，将地址操作数和段基的总和提供给翻译后备缓冲器（TLB），该翻译后备缓冲器存储相同的翻译格式（和和携带）。在另一个实施例中，AGU基于进位来校正所生成的和的最高有效位。 AGU和/或TLB可以在处理指令集架构中定义的16位寻址模式时提供减少的地址生成等待时间。

10. 发明授权

US5695389A Blasting device with oscillating nozzle 失效
标题翻译：带振动喷嘴的喷砂装置
公开(公告)号：US5695389A
公开(公告)日：1997-12-09
申请号：US583788
申请日：1996-01-11
申请人： J. Christian Bartel , William A. McGee , Anthony P. Duracensky
发明人： J. Christian Bartel , William A. McGee , Anthony P. Duracensky
IPC分类号： B24C3/06
CPC分类号： B24C3/067
摘要： A blasting device for directed air with entrained blast media at a work surface includes a frame supporting a reciprocal valve, and an adjustable valve limit switch. A shaft is attached to the reciprocal valve at one end, and is supported via a bearing assembly at the other end with a blast nozzle mounted thereto. Rotation of the reciprocal valve causes rotation of the interconnected blast nozzle such that air with entrained blast media exiting the blast nozzle travels along a path beneath the frame. The frame is supported on wheels, and is moved along a work surface by an operator. A vacuum port is positioned adjacent the work surface for removing spent blast media with entrained debris from beneath the blasting device. The handle may be rotated from end to end for ease of operation to assure that the user may move the blasting device in either the forward or rearward direction along a work surface.
摘要翻译：用于在工作表面具有夹带的鼓风介质的定向空气的喷砂装置包括支撑往复阀的框架和可调节的阀限位开关。轴在一端附接到往复阀，并且在另一端通过安装在其上的鼓风喷嘴的轴承组件支撑。往复阀的旋转导致互连的喷嘴的旋转，使得离开喷嘴的夹带的鼓风介质的空气沿着框架下方的路径行进。框架支撑在车轮上，并且由操作者沿工作表面移动。真空端口邻近工作表面定位，用于从喷砂装置下方移除带有夹带的碎屑的废弃鼓风介质。手柄可以从端到端旋转以便于操作以确保使用者可以沿着工作表面向前或向后方向移动喷砂装置。

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