专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2023032470A1 適応フィルタ装置、適応フィルタ方法、および適応フィルタプログラム审中-公开
公开(公告)号：WO2023032470A1
公开(公告)日：2023-03-09
申请号：PCT/JP2022/027330
申请日：2022-07-11
申请人：旭化成エレクトロニクス株式会社
发明人：市原　栄蔵 , 甲斐　佑介
IPC分类号： H03H21/00 , H03H17/00 , H03H17/06
摘要：入力信号をダウンサンプリングした出力信号を出力するデシメーションフィルタと、入力信号の特性に基づいて、デシメーションフィルタの次数を調整するフィルタ制御部とを備える適応フィルタ装置を提供する。

2. 发明申请

WO2022140606A1 HIGH-PERFORMANCE FILTER BANK CHANNELIZERS 审中-公开
公开(公告)号：WO2022140606A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/064955
申请日：2021-12-22
申请人： SPECTRAL DSP CORP
发明人： HARRIS, Fredric, J.
IPC分类号： H03H19/00 , H03H17/00
摘要： High-performance filter bank channelizers are provided. In one embodiment, a heterodyne signal shifts an input spectrum of the input signal by an offset between input and output centers, and operates at a high input sample rate. In another embodiment, the channelizer includes an input commutator receiving and commutating an input signal, an M-path polyphaser filter in communication with the commutator, and an M-path inverse discrete Fourier transform module processing outputs of the polyphaser filter, wherein the M-path polyphaser filter introduces a plurality of phase rotations in a time domain resulting in a workload reduction for a processor on which the channelizer is implemented. Still other embodiments includes a resampling channelizer, a half-band filter, and a cascaded half-band filter.

3. 发明申请

WO2016060497A1 위상 180도로 정렬한 1차 측파대 필터들을 이용하고 측파대 차동출력 비교기들의 위상을 맞춰 지터를 줄인 저전력용 광대역 비동기식 이산 위상 편이 복조 회로 审中-公开
标题翻译：低功率宽带异步二进制相移键控解调电路，使用基于180°相位并具有减少抖动的主边界滤波器，根据边带差分输出比较器的相位
公开(公告)号：WO2016060497A1
公开(公告)日：2016-04-21
申请号：PCT/KR2015/010904
申请日：2015-10-15
申请人： 윌커슨벤자민피
发明人： 윌커슨벤자민피
IPC分类号： H04L27/233 , H03H17/00
CPC分类号： H04L27/233 , H03K5/2481 , H03K19/01728 , H03K19/01855 , H03K19/0963 , H04L7/0278 , H04L27/2331 , H04L27/2334 , H04L27/2335 , H04W4/80
摘要： 본 발명의 실시예는 저전력용 광대역 비동기식 BPSK 복조 방법과 그 회로의 구성에 관한 것이다. BPSK 복조 회로의 구성에 있어서, 변조된 신호를 차단 주파수가 캐리어 주파수인 1차 고역 필터와 1차 저역 필터로 상측파대와 하측파대로 분리하여 정위상과 부위상으로 디지털화하는데 하측파대 비교기의 디지털 출력을 상측파대 비교기의 디지털 출력과 정반대 위상인 신호들이 심볼엣지와 심볼엣지 사이에서 같은 상승엣지와 같은 하강엣지에서 각각 비교되게 함으로써 최대로 지터를 줄여 수율을 높이면서 하측파대 디지털 신호들을 캐리어 주파수의 1/4 주기만큼 지연시킨 하측파대 디지털 신호들과 상측파대 디지털 신호들을 출력하는 측파대 분리 및 하측파대 신호지연부; 지연된 하측파대 정위상 디지털 신호와 상측파대 부위상 디지털 신호의 위상차이를 180 o 로 정렬시켜 검출한 제1 심볼엣지 신호를 생성하고, 상기 지연된 하측파대 부위상 디지털 신호와 상측파대 정위상 디지털 신호의 위상차이를 180 o 로 정렬시켜 검출한 제2 심볼엣지 신호를 생성하고, AND 게이트를 통해 제1 심볼엣지 신호와 제2 심볼엣지 신호를 겹치게 함으로써 글리치를 줄이고 디글리치 필터를 통해 글리치가 없는 심볼엣지 클럭을 생성하고, 상기 지연된 하측파대 정위상 디지털 신호를 상기 심볼엣지 신호의 하강 엣지에 동기함으로써 데이터를 복조하는 데이터 복조부; 및 상기 지연된 하측파대 정위상 디지털 신호와 상기 복조된 데이터 신호를 이용하여 데이터 클럭을 발생하는 데이터 클럭 복원부를 포함하는 저전력용 광대역 비동기식 이산 위상 편이 복조 회로가 제공될 수 있다.
摘要翻译：本发明的实施例涉及一种低功率宽带异步BPSK解调方法及其电路结构。关于BPSK解调电路的配置，可以提供一种低功率宽带异步二进制移相键控解调电路，包括：边带分离和下边带信号延迟单元，用于将调制信号分离成上边带和下边带边带使用具有载波频率作为其截止频率的初级高通滤波器和初级低通滤波器，并将其数字化为正相和负相位，使得结合来自下边带的数字输出比较器和来自上边带比较器的数字输出，分别在符号边缘和另一个符号边沿之间的相同上升沿和相同下降沿比较具有相反相位的信号，从而最大程度地减少抖动，提高产量比例，并输出下边带数字信号和上边带数字信号，下边带数字信号已经延迟了载波频率的1/4频率; 数据解调单元，用于产生通过将延迟的下边带正相数字信号和上边带负相位数字信号之间的相位差对准为180度而检测的第一符号边缘信号，并产生通过对准检测到的第二符号边缘信号延迟低边带负相数字信号与上边带正相数字信号之间的相位差为180°，数据解调单元通过与门与第一符号边沿信号和第二符号边缘信号重叠，从而减少毛刺产生通过去离子滤波器没有毛刺的符号边缘时钟，数据解调单元将延迟的下边带正相数字信号与符号边缘信号的下降沿同步，从而解调数据; 以及数据时钟恢复单元，用于使用延迟的下边带正相数字信号和解调数据信号产生数据时钟。

4. 发明申请

WO2015140113A1 REALIZATION OF RECURSIVE DIGITAL FILTERS ON PARALLEL COMPUTING PLATFORMS 审中-公开
标题翻译：在平行计算平台上实现数字滤波器
公开(公告)号：WO2015140113A1
公开(公告)日：2015-09-24
申请号：PCT/EP2015/055455
申请日：2015-03-16
申请人： THOMSON LICENSING
发明人： SCHMIDT, Jürgen
IPC分类号： G10H22/00 , H03H17/00 , G06F9/50
CPC分类号： G06F9/544 , G06F9/5016 , G06F9/5066 , G10H2250/121 , H03H17/04
摘要： A method for implementing an IIR filter (100) on a parallel processing hardware platform (200) such as a GPU (340), comprises separating the IIR filter into a sequence of biquad filters (110), implementing each biquad filter as a separate thread (120) with one or more processing elements (130) each, assigning to the first thread a first output memory block (140), and to the last thread a first input memory block (150), assigning to each of the remaining threads an input memory block (150) and an output memory block (140), executing each of the threads with a first block of data (160) to be processed, and when all threads (120) are finished, assigning to the first thread a different second output memory block and to the last thread a different second input memory block, assigning to each of the remaining threads a different input memory block and a different output memory block than before, such that each output memory block of a thread becomes a new input memory block of the next thread, and each input memory block of a thread becomes a new output memory block of the previous thread, and executing each of the threads with a second block of data (160) to be processed. The above steps are repeated for all blocks of the data to be processed.
摘要翻译：在诸如GPU（340）的并行处理硬件平台（200）上实现IIR滤波器（100）的方法包括将IIR滤波器分成二级过滤器（110）序列，将每个二叉滤波器实现为单独的线程（120），每个具有一个或多个处理元件（130），向第一线程分配第一输出存储器块（140），并向最后线程分配第一输入存储器块（150），向每个剩余线程分配输入存储器块（150）和输出存储器块（140），用要处理的第一数据块（160）执行每个线程，并且当所有线程（120）完成时，向第一线程分配不同的第二输出存储器块和最后一个线程不同的第二输入存储器块，向每个剩余线程分配不同于以前的不同输入存储器块和不同的输出存储器块，使得线程的每个输出存储器块变为新的输入记忆块的下一个threa d，并且线程的每个输入存储器块变为先前线程的新的输出存储器块，并且用要处理的第二数据块（160）执行每个线程。对要处理的数据的所有块重复上述步骤。

5. 发明申请

WO2014168100A1 携帯型生体信号送信装置、生体信号伝送方法およびデジタルフィルタ审中-公开
标题翻译：便携式BIOSIGNAL传输设备，BIOSIGNAL传输方法和数字滤波器
公开(公告)号：WO2014168100A1
公开(公告)日：2014-10-16
申请号：PCT/JP2014/060050
申请日：2014-04-07
申请人：トヨタテクニカルディベロップメント株式会社
发明人：森田　博名 , 岡田　幸泰 , 飯田　一輝 , 成田　義之
IPC分类号： A61B5/04 , A61B5/00 , H03H17/00
CPC分类号： A61B5/7225 , A61B5/0024
摘要：　複数チャンネルの生体信号をリアルタイムに無線通信によって伝送する。　生体信号を入力する複数のアナログセンサ部と、前記生体信号をデジタル生体信号に変換する複数のADコンバータと、前記デジタル生体信号の所定の帯域成分を除去するバンドパスフィルタと、前記バンドパスフィルタから出力されるデジタル生体信号を移動平均する移動平均フィルタと、前記移動平均フィルタから出力される前記デジタル生体信号の周波数を変換する周波数変換部と、前記周波数変換部から出力される前記デジタル生体信号を無線送信する通信部と、を備える携帯型生体信号送信装置。
摘要翻译：来自多个通道的生物信号通过无线通信实时传输。便携式生物信号传输装置包括：输入生物信号的多个模拟传感器单元; 将生物信号转换为数字生物信号的多个AD转换器; 带通滤波器，其去除数字生物信号的预定带宽分量; 移动平均滤波器，其对从带通滤波器输出的数字生物信号执行移动平均; 频率转换单元，其转换从移动平均滤波器输出的数字生物信号的频率; 以及无线地传送从变频单元输出的数字生物信号的通信单元。

6. 发明申请

WO2012142703A1 DIGITAL EMI FILTER 审中-公开
标题翻译：数字电磁滤波器
公开(公告)号：WO2012142703A1
公开(公告)日：2012-10-26
申请号：PCT/CA2012/000374
申请日：2012-04-19
申请人： QUEEN'S UNIVERSITY AT KINGSTON , HAMZA, Djilali , JAIN, Praveen K.
发明人： HAMZA, Djilali , JAIN, Praveen K.
IPC分类号： H02M1/44 , H03H17/00
CPC分类号： H02M1/44 , H02M1/12
摘要： The invention provides a digital active EMI filter that removes, minimizes, or reduces unwanted interference (i.e., EMI noise) generated by a power circuit such as, for example, a power converter. Digital active filtering includes digital sampling of the incident noise signal amplitude and frequency, discrete time conversion of the EMI noise source, processing (e.g., inverting) the digital signal, and then constructing an analog output signal (i.e., an EMI compensation signal) which is injected to the input of the power circuit. A digital EMI filter as described herein may be used in both differential-mode and common-mode configurations, and overcomes limitations of passive and active analog EMI filters.
摘要翻译：本发明提供一种数字有源EMI滤波器，其去除，最小化或减少由例如功率转换器的电力电路产生的不需要的干扰（即，EMI噪声）。数字有源滤波包括入射噪声信号幅度和频率的数字采样，EMI噪声源的离散时间转换，数字信号的处理（例如，反相），然后构建模拟输出信号（即EMI补偿信号），其中被注入到电源电路的输入端。这里描述的数字EMI滤波器可以用于差模和共模配置，并克服无源和有源模拟EMI滤波器的限制。

7. 发明申请

WO2011100868A1 FILTER DEVICE AND METHOD FOR PROVIDING A FILTER DEVICE 审中-公开
标题翻译：用于提供过滤装置的过滤装置和方法
公开(公告)号：WO2011100868A1
公开(公告)日：2011-08-25
申请号：PCT/CN2010/070695
申请日：2010-02-20
申请人： HUAWEI TECHNOLOGIES CO., LTD. , XIE, Changsong , FABIAN, Nikolaus Hauske
发明人： XIE, Changsong , FABIAN, Nikolaus Hauske
IPC分类号： H03H17/00
CPC分类号： H03H17/06 , H03H17/0294 , H03H2220/08
摘要： The invention relates to a filter device (200) for filtering an input signal (s(t)). The filter device (200) has a plurality of taps (210-216) having a respective filter coefficient (w 0 -w 6 ) and a plurality of delay elements (221-226), wherein at least two delay elements (221-226) have different delays.
摘要翻译：本发明涉及一种用于滤波输入信号（s（t））的滤波器装置（200）。滤波器装置（200）具有多个具有相应滤波器系数（w0-w6）和多个延迟元件（221-226）的抽头（210-216），其中至少两个延迟元件（221-226）具有不同的延误。

8. 发明申请

WO2010111619A3 VOLTAGE MODE TRANSMITTER EQUALIZER 审中-公开
标题翻译：电压模式发射机均衡器
公开(公告)号：WO2010111619A3
公开(公告)日：2011-01-27
申请号：PCT/US2010028871
申请日：2010-03-26
申请人： RAMBUS INC , DETTLOFF WAYNE D , POULTON JOHN W , WILSON JOHN M
发明人： DETTLOFF WAYNE D , POULTON JOHN W , WILSON JOHN M
IPC分类号： H04L25/03 , H03H17/00 , H03H21/00 , H03K19/0175 , H04L25/02
CPC分类号： H04L25/03343 , H04L25/0272 , H04L25/0278 , H04L25/03885
摘要： A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.
摘要翻译：电压模式发射机均衡器具有高效率，但是从电源消耗基本恒定的电源电流并提供恒定的反匹配阻抗。电压模式发射机均衡器被配置为使得可以根据输入数据来控制要在一对传输线上输出的信号的输出电压，但是其返回阻抗基本上与传输线的差分阻抗匹配，并且它无论信号的输出电压如何，都能从电源中抽取大致恒定的电源电流。此外，用于电压模式发射机的均衡器通过采用可变上拉电导和可变下拉电导来提供细粒度均衡设置。通过选择性地启用多个电导通道来改变电导，其中至少一些导电通道具有彼此不同的电阻值。

9. 发明申请

WO2010088293A2 CHANNEL SELECT FILTER APPARATUS AND METHOD 审中-公开
标题翻译：通道选择滤波器和方法
公开(公告)号：WO2010088293A2
公开(公告)日：2010-08-05
申请号：PCT/US2010022266
申请日：2010-01-27
申请人： ESS TECHNOLOGY INC , MALLINSON ANDREW MARTIN
发明人： MALLINSON ANDREW MARTIN
IPC分类号： H03H17/00
CPC分类号： H03H17/0248 , B60N2/002 , H03H15/00 , H03M1/687 , H03M1/745 , H03M1/747
摘要： Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non- radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital- to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
摘要翻译：描述通道选择滤波器电路。一个电路实现了一个乘法元件和数模转换器作为差分电流模式器件。实现乘法元件和数模转换器的另一个电路，具有加权相加，在数模转换器和乘法器组合相乘后延迟。在一个这样的电路中，基本相等的电流源幅度在电路的不同列中。另一个具有基本相等的电流源幅度的这种电路使用非基2。具有基本相等的电流源幅度的另一个这样的电路具有部分分割。另一电路实现了乘法元件和数模转换器，具有部分分段，元件的加扰位分配。如这里所述，一个这样的电路对等加权的片段进行比特分配。另一个电路实现了具有选择性地启用重复的电流源装置的乘法元件和数模转换器。另一电路实现了具有可变有效长度的数模转换器的乘法元件和数模转换器。在一个这样的电路中，如本文所述，乘法器元件的一个或多个电流源被取消选择以去除乘法器元件的噪声贡献。复合滤波电路包括一对实际有限脉冲响应滤波器电路，在当前域进行加法和减法，共享公共电阻网络以执行加权相加。一个这样的电路还包括第二对实际有限脉冲响应滤波器电路，其在当前域中执行加法和减法，共享第二公共电阻器网络以执行加权相加。

10. 发明申请

WO2008085448A1 COMMON MODE ADAPTIVE EQUALIZATION 审中-公开
标题翻译：共模自适应均衡
公开(公告)号：WO2008085448A1
公开(公告)日：2008-07-17
申请号：PCT/US2007/026278
申请日：2007-12-20
申请人： INTEL CORPORATION , MELLITZ, Richard
发明人： MELLITZ, Richard
IPC分类号： H04B3/04 , H03H17/00
CPC分类号： H04L25/03885
摘要： In some embodiments common mode equalization is performed on a received differential signal to produce a voltage signal that is proportional to a common mode voltage of the differential signal. A command signal is provided in response to the common mode equalization to adjust a delay between two pairs of the differential signal. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，对所接收的差分信号执行共模均衡以产生与差分信号的共模电压成正比的电压信号。响应于共模均衡来提供命令信号以调整两对差分信号之间的延迟。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式