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1. 发明申请

WO2023004947A1 字线驱动器电路及存储器审中-公开
公开(公告)号：WO2023004947A1
公开(公告)日：2023-02-02
申请号：PCT/CN2021/117277
申请日：2021-09-08
申请人：长鑫存储技术有限公司
发明人：杨桂芬
IPC分类号： G11C5/02 , G11C8/08
摘要：本申请实施例涉及半导体领域，提供一种字线驱动器电路及存储器，字线驱动器电路至少可以包括：多个字线驱动器，每一字线驱动器包含对应的PMOS管和NMOS管，多个字线驱动器包含的多个PMOS管并排设置，多个字线驱动器包含的多个NMOS管并排设置，在PMOS管的排列方向上，多个PMOS管位于多个NMOS管的同一侧。

2. 发明申请

WO2022271484A1 WEAK PRECHARGE BEFORE WRITE DUAL-RAIL SRAM WRITE OPTIMIZATION 审中-公开
公开(公告)号：WO2022271484A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/033402
申请日：2022-06-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： AHMED, Tawfik , ROBISON, Andrew, J. , SCHREIBER, Russell, J.
IPC分类号： G11C11/419 , G11C11/412 , G11C7/12 , G11C8/08 , G11C11/418
摘要： A method for accessing a memory cell includes enabling precharging of a bit line of the memory cell before a next access of the memory cell. The method includes disabling the precharging after a first interval if the next access is a write. The method includes disabling the precharging after a second interval if the next access is a read. The first interval is shorter than the second interval.

3. 发明申请

WO2022226474A1 PARALLEL DRIFT CANCELLATION 审中-公开
公开(公告)号：WO2022226474A1
公开(公告)日：2022-10-27
申请号：PCT/US2022/071719
申请日：2022-04-14
申请人： MICRON TECHNOLOGY, INC.
发明人： PELLIZZER, Fabio
IPC分类号： G11C8/08 , G11C13/00
摘要： Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.

4. 发明申请

WO2021158249A1 POWER MANAGEMENT FOR MULTI-PLANE READ OPERATIONS 审中-公开
公开(公告)号：WO2021158249A1
公开(公告)日：2021-08-12
申请号：PCT/US2020/035019
申请日：2020-05-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： LIEN, Yu-Chung , ELIASH, Tomer , TSENG, Huai-Yuan
IPC分类号： G06F3/06 , G11C8/08
摘要： Apparatuses and techniques are described for managing power consumption in a memory device. When a multi -plane read command is received, a control circuit determines whether the blocks identified by the read command are fully or partially programmed. If they are fully programmed, the read command is executed while applying a common read pass voltage to the unprogrammed word lines of the respective blocks. If the blocks are not all fully programmed, the control circuit determines a last-programmed word line. If the last-programmed word lines are not equal in each block, the read command is executed while applying a base read pass voltage to the unprogrammed word lines of one or more higher-programmed blocks and a lower read pass voltage to the unprogrammed word lines of one or more lower-programmed blocks.

5. 发明申请

WO2021080830A1 READ SPIKE MITIGATION IN INTEGRATED CIRCUIT MEMORY 审中-公开
公开(公告)号：WO2021080830A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/055565
申请日：2020-10-14
申请人： MICRON TECHNOLOGY, INC.
发明人： HAMADA, Josephine Tiu , SURDYK, Kenneth Richard , YANG, Lingming , CUI, Mingdong
IPC分类号： G11C13/00 , G11C8/08
摘要： An integrated circuit memory device, having: a first wire; a second wire; a memory cell connected between the first wire and the second wire; a first voltage driver connected to the first wire; and a second voltage driver connected to the second wire. During an operation to read the memory cell, the second voltage driver is configured to start ramping up a voltage applied on the second wire after the first voltage driver starts ramping up and holding a voltage applied on the first wire.

6. 发明申请

WO2021022757A1 字线驱动电路及存储单元审中-公开
公开(公告)号：WO2021022757A1
公开(公告)日：2021-02-11
申请号：PCT/CN2019/126394
申请日：2019-12-18
申请人：长鑫存储技术有限公司
发明人：刘志拯
IPC分类号： G11C8/08 , G11C16/08
摘要：涉及存储技术领域，提出一种字线驱动电路，该字线驱动电路包括开关晶体管（T5）和环形振荡器（1），所述开关晶体管（T5）的控制端连接第一控制信号端（VCN1），所述开关晶体管（T5）的第一端连接驱动电压端（LWL），所述开关晶体管（T5）的第二端连接字线信号端（WL）；所述环形振荡器的电源端接所述字线信号端（WL），所述环形振荡器（1）的接地端（GND）为所述字线驱动电路的接地端。提供的字线驱动电路可以增强其器件可靠性和寿命。

7. 发明申请

WO2020185469A1 IMPROVED ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL 审中-公开
公开(公告)号：WO2020185469A1
公开(公告)日：2020-09-17
申请号：PCT/US2020/021015
申请日：2020-03-04
申请人： QUALCOMM INCORPORATED
发明人： RAJ, Pradeep , SAHU, Rahul , GUPTA, Sharad Kumar
IPC分类号： G11C8/08 , G11C7/22 , G11C8/18 , G11C11/413 , G11C11/418
摘要： Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

8. 发明申请

WO2018208445A1 SENSE AMPLIFIER SIGNAL BOOST 审中-公开
公开(公告)号：WO2018208445A1
公开(公告)日：2018-11-15
申请号：PCT/US2018/028085
申请日：2018-04-18
申请人： MICRON TECHNOLOGY, INC.
发明人： INGALLS, Charles , KAWAMURA, Christopher
IPC分类号： G11C7/06 , G11C8/08
摘要： Apparatuses for signal boost are disclosed, an example apparatus includes: first and second digit lines coupled to memory cells; a sense amplifier including: first and second transistors having gates operatively coupled to the first digit line and drains coupled to a first node, sources of the first and second transistors coupled to first and second control lines providing first and second power supply voltage respectively; and third and fourth transistors having gates coupled to the second digit line and drains coupled to a second node, sources of the third and fourth transistors coupled to the first and second control lines respectively; a power line coupled to the first node and the second node; and a power switch providing either the first power supply voltage or a third power supply voltage smaller than the first power supply voltage to the power line.

9. 发明申请

WO2017131941A1 MEMORY CELL SCREEN FOR BTI EFFECT 审中-公开
标题翻译：存储单元屏幕用于BTI效果
公开(公告)号：WO2017131941A1
公开(公告)日：2017-08-03
申请号：PCT/US2017/012710
申请日：2017-01-09
申请人： QUALCOMM INCORPORATED
发明人： JUNG, Chulmin , AHMED, Fahad , YOON, Sei Seung , KIM, Keejong
IPC分类号： G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418 , G11C29/12
CPC分类号： G11C11/419 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/417 , G11C11/418 , G11C29/12005 , G11C2029/1202
摘要： A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.
摘要翻译：提供了一种用于操作存储器的存储器和方法。该存储器包括多个存储器单元和被配置为输出字线的字线驱动器。存储器单元耦合到字线。控制电路被配置为向存储单元和字线驱动器提供工作电压。电压调节电路被配置为在控制电路向存储单元和字线驱动器提供工作电压期间调节提供给存储单元的工作电压。该方法包括向至少一个存储器单元和耦合到至少一个存储器单元的字线供应工作电压，并且在向至少一个存储器提供工作电压期间调节提供给至少一个存储器单元的工作电压细胞和字线。

10. 发明申请

WO2017127193A1 STATIC RANDOM ACCESS MEMORY WITH IMPROVED WRITE TIME AND REDUCED WRITE POWER 审中-公开
标题翻译：静态随机访问存储器，改进了写入时间，减少了写入功耗
公开(公告)号：WO2017127193A1
公开(公告)日：2017-07-27
申请号：PCT/US2016/067348
申请日：2016-12-16
申请人： QUALCOMM INCORPORATED
发明人： GUPTA, Sharad Kumar , NARASIMHAN, Mukund , BODA, Veerabhadra Rao
IPC分类号： G11C11/418 , G11C8/18 , G11C8/10 , G11C8/08 , G11C7/22
CPC分类号： G11C7/227 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10 , G11C8/18 , G11C11/418 , G11C11/419 , G11C2207/229
摘要： A static random access memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.
摘要翻译：提供一种静态随机存取存储器，其中写入操作期间的字线断言被延迟直到检测到虚拟位线的放电为止。

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