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1. 发明申请

WO1998028849A1 A DIGITAL PHASE-LOCKED LOOP AND A METHOD OF CONTROLLING IT, AS WELL AS A METHOD AND RECEIVER CIRCUIT FOR DESYNCHRONIZATION IN A DIGITAL TRANSMISSION SYSTEM 审中-公开
标题翻译：一种数字锁相环及其控制方法，以及数字传输系统中用于解密的方法和接收电路
公开(公告)号：WO1998028849A1
公开(公告)日：1998-07-02
申请号：PCT/DK1997000594
申请日：1997-12-22
申请人： DSC COMMUNICATIONS A/S , THOMSEN, Per, H.
发明人： DSC COMMUNICATIONS A/S
IPC分类号： H03L07/085
CPC分类号： H04J3/076 , H03L7/093
摘要： A digital phase-locked loop comprises a numerically controlled oscillator (5) which is capable of generating a clock signal by dividing a system clock frequency by a factor determined by a control word, and a phase detector (2; 3) which is capable of generating the control word in response to a phase difference between the clock signal and an external reference signal so that the control word assumes a nominal value when the phase difference is numerically smaller than a given value, and may assume one or more other values when the phase difference is numerically greater than the given value. The loop moreover comprises means (7) which, when the phase difference is numerically greater than the given value, may modulate the control word. A corresponding method is also disclosed. The digital phase-locked loop may be used in a receiver circuit for a digital transmission system in connection with desynchronization of data signals.
摘要翻译：数字锁相环包括数控振荡器（5），其能够通过将系统时钟频率除以由控制字确定的因子来产生时钟信号;以及相位检测器（2; 3），其能够响应于时钟信号和外部参考信号之间的相位差产生控制字，使得当相位差在数值上小于给定值时，控制字采用标称值，并且当该时钟信号与外部参考信号之间存在一个或多个其它值时相位差在数值上大于给定值。该环路还包括装置（7），当相位差在数值上大于给定值时，可以调制控制字。还公开了相应的方法。数字锁相环可以用于与数据信号的去同步相关的数字传输系统的接收机电路中。

2. 发明申请

WO1994029964A1 PROCESS FOR ENHANCING THE NOISE IMMUNITY OF A PHASE-LOCKED LOOP AND DEVICE FOR APPLYING SAME. 审中-公开
标题翻译：用于增强相位锁定环路的噪声免疫的方法及其应用的装置。
公开(公告)号：WO1994029964A1
公开(公告)日：1994-12-22
申请号：PCT/FR1994000659
申请日：1994-06-03
申请人： THOMSON CONSUMER ELECTRONICS , DELMAS, Christian , PAILLARDET, Frédéric , DELL'OVA, Francis
发明人： THOMSON CONSUMER ELECTRONICS
IPC分类号： H03L07/085
CPC分类号： H04N5/126 , H03L7/085 , H03L7/0891 , H03L7/14 , H03L7/191
摘要： Process for enhancing the noise immunity of a phase-locked loop vhich comprises a comparator (9), and means (14) for inhibiting the action of said comparator on said phase-locked loop. The process is characterized in that said inhibition is cancelled during a main time window resulting from the intersection of a first time window established from the phase-locked loop input signal and of a second time window established from the loop return signal. The invention is useful in the field of video.
摘要翻译：用于增强锁相环的抗噪声性的方法包括比较器（9）和用于禁止所述比较器对所述锁相环的动作的装置（14）。该过程的特征在于，在由从锁相环输入信号建立的第一时间窗口和从循环返回信号建立的第二时间窗口的交点产生的主时间窗口期间，所述抑制被抵消。本发明在视频领域中是有用的。

3. 发明申请

WO1997039529A1 A DIGITAL AUDIO RESOLVING APPARATUS AND METHOD 审中-公开
标题翻译：数字音频解决方案和方法
公开(公告)号：WO1997039529A1
公开(公告)日：1997-10-23
申请号：PCT/US1997006488
申请日：1997-04-11
申请人： AVID TECHNOLOGY, INC.
发明人： AVID TECHNOLOGY, INC. , MOCK, Jeffrey, C.
IPC分类号： H03L07/085
CPC分类号： H03L7/181 , H03L7/085 , H03L7/0994 , H03L7/143
摘要： A resolving system for providing an output clock signal having an output clock frequency that is a predetermined rational multiple of a clock frequency of an input signal to the resolving system. In one embodiment, the resolving system includes a first counter (122) that counts clock pulses of the input clock signal to provide a first value, a second counter (124) that counts clock pulses of the output clock signal to provide a second value, a processor (123) that computes a difference between a ratio of the second and first values with the predetermined rational multiple and generates an error signal based on the difference, and a direct digital synthesis unit (120) that receives the error signal, and based on the error signal generates the output clock signal. In another embodiment, the resolving system, in the absence of an input signal, controls the direct digital synthesis unit to generate the output clock signal at a predetermined frequency.
摘要翻译：一种分辨系统，用于提供具有输出时钟频率的输出时钟信号，该输出时钟频率是输入信号的时钟频率的预定有理倍数。在一个实施例中，分辨系统包括：计数输入时钟信号的时钟脉冲以提供第一值的第一计数器（122）;计数输出时钟信号的时钟脉冲以提供第二值的第二计数器（124）计算第二值和第一值与预定有理倍数之间的差异的处理器（123），并且基于该差异产生误差信号;以及直接数字合成单元（120），其接收误差信号，并基于误差信号产生输出时钟信号。在另一个实施例中，分辨系统在没有输入信号的情况下控制直接数字合成单元以预定频率产生输出时钟信号。

4. 发明申请

WO1996021973A1 A PHASE ERROR PROCESSOR CIRCUIT WITH A COMPARATOR INPUT SWAPPING TECHNIQUE 审中-公开
标题翻译：具有比较器输入切换技术的相位错误处理器电路
公开(公告)号：WO1996021973A1
公开(公告)日：1996-07-18
申请号：PCT/US1995016834
申请日：1995-12-20
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , WONG, Hee , LI, Gabriel, M.
IPC分类号： H03L07/085
CPC分类号： H03L7/085 , H03L7/0991 , H04L7/0083 , H04L7/033
摘要： A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs off a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams. The output of the exclusive-OR gate is coupled to the input of a D flip flop which is latched once per window. The output of the D flip flop is an UP/ DOWN signal which controls an oscillator, which generates the local clock signal, to advance or retard the phase of the local clock in response to the condition of the UP/ DOWN signal.
摘要翻译：一种具有相位误差处理器（PEP）电路的锁相环，其中以第一脉冲流的形式向PEP电路提供相位误差，该第一脉冲流包括由输入数据和本地信号之间的相位误差指定的宽度的脉冲时钟和包括参考宽度的脉冲的第二脉冲流。电路包括两个积分器，分别具有耦合到比较器的第一和第二输入的输出。在第一时间窗口期间，开关将第一脉冲流耦合到一个积分器的输入，将第二脉冲流耦合到另一个积分器的输入端，并在第二时间窗口期间反向连接。开关由SWAP信号控制，SWAP信号以规则的间隔交替状态。比较器的输出与SWAP信号异或，以便每隔一个窗口反相比较器输出信号，以便平均比较器的任何输入偏移误差或由于两个脉冲流之间的积分器不匹配引起的偏移。异或门的输出耦合到D触发器的输入，每个窗口被锁存一次。 D触发器的输出是UP / DOWN信号，其控制产生本地时钟信号的振荡器，以响应于UP的状态推进或延迟本地时钟的相位 / DOWN 信号。

5. 发明申请

WO1995016309A1 D/A FOR CONTROLLING AN OSCILLATOR IN A PHASE LOCKED LOOP 审中-公开
标题翻译：用于在相位锁定环路中控制振荡器的D / A
公开(公告)号：WO1995016309A1
公开(公告)日：1995-06-15
申请号：PCT/US1993011996
申请日：1993-12-08
申请人： THOMSON CONSUMER ELECTRONICS, INC. , ROMESBURG, Eric, Douglas , RUMREICH, Mark, Francis
发明人： THOMSON CONSUMER ELECTRONICS, INC.
IPC分类号： H03L07/085
CPC分类号： H03L7/085 , H03L7/093
摘要： A phase-lock-loop circuit includes a digital-to-analog converter (60, 61, 62, 63) of the bit rate multiplier type. The input word to the converter (PHER) is updated once each horizontal period (H) of a television signal. Phase information of an output signal (BRM) of the bit rate multiplier that is obtained in one horizontal period (H) is retained for affecting the phase in the immediately following horizontal period.
摘要翻译：锁相环电路包括比特率倍增器类型的数模转换器（60,61,62,63）。转换器（PHER）的输入字每一个电视信号的每个水平周期（H）被更新一次。在一个水平周期（H）中获得的比特率乘法器的输出信号（BRM）的相位信息被保留以影响紧接着的水平周期中的相位。

6. 发明申请

WO1992022960A1 A METHOD AND AN APPARATUS FOR DETERMINING PHASE AND FREQUENCY DEVIATION 审中-公开
标题翻译：一种用于确定相位和偏差的方法和装置
公开(公告)号：WO1992022960A1
公开(公告)日：1992-12-23
申请号：PCT/DK1992000181
申请日：1992-06-12
申请人： DANCALL RADIO A/S , CETELCO A/S , MADSEN, Benny
发明人： DANCALL RADIO A/S , CETELCO A/S
IPC分类号： H03L07/085
CPC分类号： H04B1/30
摘要： In a method of determining a phase difference between two sine-shaped electrical signals, where the phase difference is known to be small and the signals are represented in a complex form, the complex conjugate value of the one signal is multiplied by the other signal, and the imaginary value of the result is used as an estimate of the phase difference between the two signals. An apparatus for the same purpose has signal paths for the two signals and comprises means which are capable of multiplying the complex conjugated value of one of the signals by the other signal, and which are capable of representing the imaginary value of the multiplication result on an output and using it as an estimate of the phase difference between the two signals.
摘要翻译：在确定两个正弦形电信号之间的相位差的方法中，其中已知相位差较小并且信号以复数形式表示，一个信号的复共轭值乘以另一个信号，并且将结果的虚数值用作两个信号之间的相位差的估计。用于相同目的的装置具有用于两个信号的信号路径，并且包括能够将其中一个信号的复共轭值乘以另一个信号的装置，并且能够将乘法结果的虚数值表示在输出并将其用作两个信号之间的相位差的估计。

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