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1. 发明申请

WO2022055076A1 자구벽 이동에 기반한 스핀 토크 다수결 게이트 审中-公开
公开(公告)号：WO2022055076A1
公开(公告)日：2022-03-17
申请号：PCT/KR2021/006900
申请日：2021-06-03
申请人： 재단법인대구경북과학기술원
发明人： 유천열 , 김우영 , 백은총
IPC分类号： H03K19/23 , H03K19/18 , H01L43/08 , H01L43/10
摘要： 본 발명은 자구벽 이동에 기반한 스핀 토크 다수결 게이트에 관한 것으로서, 일실시예에 따른 스핀 토크 다수결 게이트는 복수의 입력단과, 복수의 입력단에서 발생된 자구벽(domain wall)이 이동하는 도선과 연결되어, 자구벽의 이동에 따른 다수결 연산을 통해 출력 신호를 생성하는 홀-크로스부 및 생성된 출력 신호를 외부로 출력하는 출력단을 포함하고, 도선은 복수의 입력단으로부터 홀-크로스부로 갈수록 폭이 좁아지도록 형성될 수 있다.

2. 发明申请

WO2022003379A1 THERMAL-ELECTRIC LOGIC INTEGRATED CIRCUIT AND USE OF SAID INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2022003379A1
公开(公告)日：2022-01-06
申请号：PCT/HU2021/050038
申请日：2021-06-03
申请人： BUDAPESTI MŰSZAKI ÉS GAZDASÁGTUDOMÁNYI EGYETEM
发明人： MIZSEI, János , LAPPALAINEN, Jyrki
IPC分类号： H03K19/02 , H03K19/23
摘要： The invention is based on the integrated application of a thermal-electric active device (phonon transistor). Phonon transistors consist of resistors that respond to temperature changes with a metal-insulator phase transition, or possibly other resistors suitable for heat generation. These resistors are thermally and electrically coupled to each other as needed, and are thermally and electrically insulated from each other. The thermal-electric system built in this way is suitable for the implementation of high-integration logic networks. The switch condition of a simple majority gate is that half or more of the inputs receive a high logic level. An extended majority logic gate is a generalization of a simple majority gate, i.e. a multi-input logic circuit whose output switches to a logic high level to excite a given number of inputs. By precisely sizing the circuit and adjusting the strength of the thermal coupling, it is possible to activate a certain proportion of the input (heating) resistors in order to tilt the output. With this, the switch-on threshold can be set not only to 50% of the inputs, but also to a different value, i.e. the number of elements of the simple majority gate and the number of elements of the extended majority gate can be essentially the same. By adjusting the strength of the thermal coupling, it is also possible to take each input into account with different weights. The operation of a controlled, multimode, thermal electrical resistor-based oscillator circuit is based on the application of a negative differential resistance during metal-semiconductor switching. Complemented with a capacitor and control electronics, the switching device is able to produce stable two-level vibrations, multi-level vibrations and irregular and chaotic vibrations in various vibration modes. The grassfire algorithm performs the transformation of two-dimensional shapes. The result of the transformation will be the skeleton of the shape, which is illustratively the line of meeting of the fire front launched around the perimeter of the shape. To implement the algorithm, the devices must be switched on in a perimeter corresponding to the shape in a two-dimensional matrix (M) composed of resistors with a metal / semiconductor phase transition. Due to the heat dissipation, the adjacent devices are also switched on, the order of switching on plots the result of the algorithm.

3. 发明申请

WO2021011394A1 THRESHOLD LOGIC GATES USING FLASH TRANSISTORS 审中-公开
公开(公告)号：WO2021011394A1
公开(公告)日：2021-01-21
申请号：PCT/US2020/041653
申请日：2020-07-10
申请人： ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY , THE TEXAS A&M UNIVERSITY SYSTEM
发明人： VRUDHULA, Sarma , KHATRI, Sunil , WAGLE, Ankit
IPC分类号： H03K19/23
摘要： Threshold logic gates using flash transistors are provided. In an exemplary aspect, flash threshold logic (FTL) provides a novel circuit topology for realizing complex threshold functions. FTL cells use floating gate (flash) transistors to realize all threshold functions of a given number of variables. The use of flash transistors in the FTL cell allows a fine-grained selection of weights, which is not possible in traditional complementary metal-oxide-semiconductor (CMOS)-based threshold logic cells. Further examples include a novel approach for programming the weights of an FTL cell for a specified threshold function using a modified perceptron learning algorithm.

4. 发明申请

WO00054410A1 LOGIC CIRCUIT PROTECTED AGAINST TRANSITORY PERTURBATIONS 审中-公开
标题翻译：逻辑电路保护对抗交通事故
公开(公告)号：WO00054410A1
公开(公告)日：2000-09-14
申请号：PCT/FR2000/000573
申请日：2000-03-08
IPC分类号： G06F12/16 , G06F11/10 , H03K19/003 , H03K19/23 , H03M13/05 , H03M13/43
CPC分类号： G06F11/1497 , G06F11/10 , H03K19/00338
摘要： The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10) having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control is incorrect.
摘要翻译：本发明涉及一种防止瞬时扰动的电路，包括具有至少一个输出（A）的组合逻辑电路（10）; 产生用于所述输出的错误控制代码的电路（20）以及设置在所述输出端的存储元件（24），所述存储元件（24）由所述电路控制，所述电路在所述控制代码正确时生成要透明的控制代码，并且当控制不正确。

5. 发明申请

WO2023069074A1 METHOD AND APPARATUS OF PROGRAMMABLE QUANTIZATION/DE-QUANTIZATION ENGINE 审中-公开
公开(公告)号：WO2023069074A1
公开(公告)日：2023-04-27
申请号：PCT/US2021/055527
申请日：2021-10-19
申请人： PICOAI LIMITED , SERTILLANGE, Steven , WU, Tong , SABER, Ahmed , HU, Yujie
发明人： SERTILLANGE, Steven , WU, Tong , SABER, Ahmed , HU, Yujie
IPC分类号： H03K19/17724 , H03K19/17728 , H03K19/20 , H03K19/21 , H03K19/23
摘要： A configurable apparatus for quantization and/or de-quantization in artificial intelligence processing is disclosed. The configurable apparatus comprises an input interface configured to receive input data, an output interface configured to provide output data, a multiplier, a shifter, and an adder. The multiplier is configured to multiply data of the first multiplier input and the second multiplier input. The shifter is configured to shift data of the first shifter input according to a shift value. The first shifter input is coupled to the multiplier output. The second shifter input receives the shift value. The first multiplier input is selectively coupled to the input interface or to the adder output, and the second multiplier input is configured to receive a multiplication value. The first adder input is selectively coupled to the input interface or to the shifter output. The output interface is coupled to the shifter output or the adder output selectively.

6. 发明申请

WO2018048720A1 VOTING CIRCUITS AND METHODS FOR TRUSTED FAULT TOLERANCE OF A SYSTEM OF UNTRUSTED SUBSYSTEMS 审中-公开
标题翻译：不确定子系统的可信容错问题的投票电路和方法
公开(公告)号：WO2018048720A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/049648
申请日：2017-08-31
申请人： THE CHARLES STARK DRAPER LABORATORY, INC.
发明人： VIGEANT, Richard, L. , DE LA SERNA, Antonio, E.
IPC分类号： H03K19/23
CPC分类号： H03K19/23 , G06F11/08 , G06F13/28 , G06F13/32 , G06F21/57 , G06F21/71 , G06F2211/1097 , G07C13/02 , H03K19/0813 , H03K25/02
摘要： Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.
摘要翻译：用于确定来自多个输入的多数投票的电路和方法。示例电路包括投票输入阶段，传输阶段和累积阶段。表决输入级包括至少三个输入开关电容器。传输级包括对应于输入开关电容器的传输开关电容器。在时钟信号的状态期间，转换开关电容器对与每个输入开关电容器对应的表决电容器充电。累加级包括累加串联连接表决电容器的开关电容器。累积的开关电容器使得表决电容器的电荷在时钟信号的交替状态期间累积。表决电容器的累积电荷表示输入开关电容器的大部分投票。

7. 发明申请

WO2016071319A1 A SPIN TORQUE MAJORITY GATE DEVICE 审中-公开
标题翻译：旋转扭矩主要门控装置
公开(公告)号：WO2016071319A1
公开(公告)日：2016-05-12
申请号：PCT/EP2015/075552
申请日：2015-11-03
申请人： IMEC VZW , KATHOLIEKE UNIVERSITEIT LEUVEN KU LEUVEN R&D
发明人： VAYSSET, Adrien , RADU, Iuliana , POURTOIS, Geoffrey
IPC分类号： H03K19/23 , H03K19/18 , H01L43/08
CPC分类号： H03K19/23 , H01L43/08 , H03K19/18
摘要： A majority gate device is disclosed comprising a free ferromagnetic layer (102) comprising 3N input zones (121, 122, 123) and one polygon output zone (124) having 3N sides, each input zone adjoining the output zone and being positioned around the output zone according to a 3N-fold rotational symmetry with N being a positive integer number, whereby the input zones are spaced apart from one another by the output zone, each input zone being magnetically coupled to a corresponding input (1181, 1182, 1183) for controlling the magnetization state of the corresponding input zone, and an output sensor (119) magnetically coupled to the output zone for sensing the magnetization state of the output zone.
摘要翻译：公开了一种多数门装置，其包括包含3N输入区（121,122,123）和一个具有3N侧的一个多边形输出区（124）的自由铁磁层（102），每个输入区邻近输出区并围绕输出区域，根据3N倍的旋转对称性，其中N是正整数，由此输入区域通过输出区域彼此间隔开，每个输入区域磁耦合到相应的输入端（1181,1182,1183），用于控制相应输入区域的磁化状态，以及磁耦合到输出区域的输出传感器（119），用于感测输出区域的磁化状态。

8. 发明申请

WO1994010755A1 ELECTRONIC COMPONENT 审中-公开
标题翻译：电子元件
公开(公告)号：WO1994010755A1
公开(公告)日：1994-05-11
申请号：PCT/DE1993001039
申请日：1993-10-29
申请人： FRAUNHOFER GESELLSCHAFT ZUR FÖRDERUNG DER ... , BAUER, Norbert , BÖBEL, Friedrich , HAKEN, Hermann
发明人： FRAUNHOFER GESELLSCHAFT ZUR FÖRDERUNG DER ...
IPC分类号： H03K19/23
CPC分类号： H01L29/66992 , H01L27/15 , H01L29/36
摘要： Described is an electronic component with N input terminals, which admit N input signals, M output terminals, each of which is assigned to one or more input terminals, a component body in which, depending on the input signals, current paths or filaments are created which connect the N input terminals with the M output terminals, wherein, to establish a decision or displacement dynamics, an external quantity applied to the component switches the current flow through the component body between an initial distribution, in which the current densities (ji) between each input terminal and its assigned output terminal correspond to the input signal admitted at the respective input terminal, and a self-organizing distribution, in which the current flows only between the input terminal admitting the input signal with the highest value and its assigned output terminal.

9. 发明申请

WO1992020159A1 PROGRAMMABLE INTERCONNECT STRUCTURE FOR LOGIC BLOCKS 审中-公开
标题翻译：逻辑块可编程互连结构
公开(公告)号：WO1992020159A1
公开(公告)日：1992-11-12
申请号：PCT/US1992003575
申请日：1992-05-06
申请人： LATTICE SEMICONDUCTOR CORPORATION
发明人： LATTICE SEMICONDUCTOR CORPORATION , SHANKAR, Kapil
IPC分类号： H03K19/23
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： A structure for making programmable connections (X) between the input (I0-I7) and (O0-07) output terminals of individual logic (20, 21) blocks in a logic device is disclosed. In one embodiment, each output terminal (O0-07) is programmably connected to only one input terminal (I0-I7) of each logic block (20, 21). The same principle is followed in making connections between the input pins of the device and the input terminals of the logic blocks.

10. 发明申请

WO2022125542A1 EFFICIENT MULLER C-ELEMENT IMPLEMENTATION FOR HIGH BIT-WIDTH ASYNCHRONOUS APPLICATIONS 审中-公开
公开(公告)号：WO2022125542A1
公开(公告)日：2022-06-16
申请号：PCT/US2021/062197
申请日：2021-12-07
申请人： UNIVERSITY OF CINCINNATI [US]/[US]
发明人： EMMERT, John Martin
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/23
摘要： A system comprises an nMOS active resistor, nMOS transistors, a pMOS active resistor, and pMOS transistors, wherein a subset of the nMOS transistors a subset of the pMOS transistors are coupled to each other, respectively, according to a parallel OR configuration, a source terminal of the nMOS active resistor is coupled to respective drain terminals of the nMOS transistors, and a source terminal of the pMOS active resistor is coupled to respective drain terminals of the pMOS transistors. The transistor level delay based circuit further includes a write subcircuit component includes one of the nMOS transistors coupled to at least one of the pMOS transistors, wherein the write subcircuit is controlled by reverse logic signals, and a gate component includes an additional subset of the plurality of nMOS transistors coupled to an additional subset of the pMOS transistors, the gate component corresponding to a semistatic cross coupled inverter circuit.

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