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1. 发明申请

WO2019108284A1 I/O WRITES WITH CACHE STEERING 审中-公开
公开(公告)号：WO2019108284A1
公开(公告)日：2019-06-06
申请号：PCT/US2018/048187
申请日：2018-08-27
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： MORTON, Eric Christopher , COOPER, Elizabeth , WALKER, William L. , HUNT, Douglas Benson , BORN, Richard Martin , LEE, Richard H. , MIRANDA, Paul C. , NG, Philip
IPC分类号： G06F12/0815 , G06F12/0862
摘要： A method for steering data for an I/O write operation (144) includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric (102), a cache (122, 123, 124, 126) as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration (156) implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data via a fetch operation (152) while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

2. 发明申请

WO2013192057A1 CACHE SECTOR DIRTY BITS 审中-公开
标题翻译：高速缓存行列
公开(公告)号：WO2013192057A1
公开(公告)日：2013-12-27
申请号：PCT/US2013/046048
申请日：2013-06-16
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L.
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F12/0846 , G06F2212/1024
摘要： A cache subsystem apparatus and method of operating therefor is disclosed. In one embodiment, a cache subsystem includes a cache memory divided into a plurality of sectors each having a corresponding plurality of cache lines. Each of the plurality of sectors is associated with a sector dirty bit that, when set, indicates at least one of its corresponding plurality of cache lines is storing modified data of any other location in a memory hierarchy including the cache memory. The cache subsystem further includes a cache controller configured to, responsive to initiation of a power down procedure, determine only in sectors having a corresponding sector dirty bit set which of the corresponding plurality of cache lines is storing modified data.
摘要翻译：公开了一种用于其的缓存子系统装置及其操作方法。在一个实施例中，高速缓存子系统包括被分成多个扇区的高速缓冲存储器，每个扇区具有对应的多个高速缓存行。多个扇区中的每一个与扇区脏位相关联，当被置位时，它表示其对应的多个高速缓存行中的至少一个存储包括高速缓冲存储器的存储器层级中的任何其他位置的修改数据。高速缓存子系统还包括高速缓存控制器，其被配置为响应于断电过程的启动，仅在具有对应的扇区脏位集合的扇区中确定哪个相应的多个高速缓存行存储修改的数据。

3. 发明申请

WO2021081196A1 RING TRANSPORT EMPLOYING CLOCK WAKE SUPPRESSION 审中-公开
公开(公告)号：WO2021081196A1
公开(公告)日：2021-04-29
申请号：PCT/US2020/056851
申请日：2020-10-22
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L.
IPC分类号： G06F1/3237 , G06F1/3228 , G06F1/04
摘要： An integrated circuit (IC) device includes a ring transport having a plurality of nodes and a wire interconnect coupling the plurality of nodes in a ring. The wire interconnect including a wire to transmit clock wake signals around the ring transport in advance of data signaling representing a data packet. Each node is to switch from a clock gated state to a clocked state responsive to receiving a clock wake signal. The ring transport further includes a sleep controller coupled to a select node of the plurality of nodes. The sleep controller is to configure the select node into a clock suppression state for a specified duration responsive to identifying an idle condition on the ring transport via monitoring of the wire. While in the clock suppression state the node suppresses further transmission of any clock wake signals received at the select node.

4. 发明申请

WO2019118042A1 RINSING CACHE LINES FROM A COMMON MEMORY PAGE TO MEMORY 审中-公开
公开(公告)号：WO2019118042A1
公开(公告)日：2019-06-20
申请号：PCT/US2018/052415
申请日：2018-09-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L. , JONES, William E.
IPC分类号： G06F12/0871 , G06F12/0893
摘要： A processing system (100) rinses, from a cache (302), those cache lines (308, 309) that share the same memory page (147) as a cache line (304) identified for eviction. A cache controller (175) of the processing system identifies the cache line as scheduled for eviction. In response, the cache controller identifies additional "dirty victim" cache lines (cache lines that have been modified at the cache and not yet written back to memory) that are associated with the same memory page, and writes each of the identified cache lines to the same memory page in a memory (105). By writing each of the dirty victim cache lines associated with the memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

5. 发明申请

WO2022132795A1 PROCESSOR-GUIDED EXECUTION OF OFFLOADED INSTRUCTIONS USING FIXED FUNCTION OPERATIONS 审中-公开
公开(公告)号：WO2022132795A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/063345
申请日：2021-12-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： KALAMATIANOS, John , CLARK, Michael T. , EVERS, Marius , WALKER, William L. , MOYER, Paul , FLEISCHMAN, Jay , KOTRA, Jagadish B.
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78
摘要： Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

6. 发明申请

WO2019118016A1 MEMORY REQUEST THROTTLING TO CONSTRAIN MEMORY BANDWIDTH UTILIZATION 审中-公开
公开(公告)号：WO2019118016A1
公开(公告)日：2019-06-20
申请号：PCT/US2018/048350
申请日：2018-08-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L. , JONES, William E.
IPC分类号： G06F12/0862 , G06F12/0844
摘要： A processing system (100) includes an interconnect fabric (110) coupleable to a local memory (112) and at least one compute complex (102) coupled to the interconnect fabric. The compute complex includes a processor core (114-117) and a cache hierarchy (118). The cache hierarchy has a plurality of caches (121-130) and a throttle controller (228) configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher (220) of a cache of the cache hierarchy.

7. 发明申请

WO2019108283A1 REDUCING CACHE FOOTPRINT IN CACHE COHERENCE DIRECTORY 审中-公开
公开(公告)号：WO2019108283A1
公开(公告)日：2019-06-06
申请号：PCT/US2018/048154
申请日：2018-08-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L. , BOYER, Michael W. , ECKERT, Yasuko , LOH, Gabriel H.
IPC分类号： G06F12/0817 , G06F12/0811 , G06F11/30
摘要： A method includes monitoring, at a cache coherence directory (142), states (216) of cachelines stored in a cache hierarchy (104) of a data processing system (100) using a plurality of entries (202) of the cache coherence directory (146). Each entry of the cache coherence directory is associated with a corresponding cache page of a plurality of cache pages, and each cache page representing a corresponding set of contiguous cachelines. The method further includes selectively evicting cachelines from a first cache (300) of the cache hierarchy based on cacheline utilization densities of cache pages represented by the corresponding entries of the plurality of entries of the cache coherence directory.

8. 发明申请

WO2017222577A1 SHADOW TAG MEMORY TO MONITOR STATE OF CACHELINES AT DIFFERENT CACHE LEVEL 审中-公开
标题翻译：阴影标记存储器用于监视不同高速缓存级别的高速缓存状态
公开(公告)号：WO2017222577A1
公开(公告)日：2017-12-28
申请号：PCT/US2016/052607
申请日：2016-09-20
申请人： ADVANCED MICRO DEVICES, INC.
发明人： SRINIVASAN, Sriram , WALKER, William L.
IPC分类号： G06F12/08
摘要： A processing system (100) includes a plurality of processor cores (111, 112, 113, 114) and a plurality of private caches (131, 132, 133, 134). Each private cache is associated with a corresponding processor core of the plurality of processor cores and includes a corresponding first set of cachelines. The processing system further includes a shared cache (140) shared by the plurality of processor cores. The shared cache includes a second set of cachelines, and a shadow tag memory (142) including a plurality of entries (216), each entry storing state information (215) for a corresponding cacheline of the first set of cachelines of one of the private caches.
摘要翻译：处理系统（100）包括多个处理器核（111,112,113,114）和多个专用高速缓存（131,132,133,134）。每个专用高速缓存与多个处理器内核中的对应处理器内核相关联并且包括对应的第一组高速缓存行。处理系统还包括由多个处理器核共享的共享高速缓存（140）。所述共享高速缓存包括第二组高速缓存行和包括多个条目（216）的影子标签存储器（142），每个条目存储用于所述私有设备中的一个的第一组高速缓存行的对应高速缓存行的状态信息（215）高速缓存。

9. 发明申请

WO2019089142A1 RETAINING CACHE ENTRIES OF A PROCESSOR CORE DURING A POWERED-DOWN STATE 审中-公开
公开(公告)号：WO2019089142A1
公开(公告)日：2019-05-09
申请号：PCT/US2018/051157
申请日：2018-09-14
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L. , GOLDEN, Michael L. , EVERS, Marius
IPC分类号： G06F12/0891 , G06F12/02 , G06F12/0811 , G06F12/0862
摘要： A processor core (215) associated with a first cache (205) initiates entry into a powered-down state. In response, information representing a set of entries (220) of the first cache are stored in a retention region (230) that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.

10. 发明申请

WO2018048748A1 SYSTEMS AND METHOD FOR DELAYED CACHE UTILIZATION 审中-公开
标题翻译：用于延迟高速缓存利用的系统和方法
公开(公告)号：WO2018048748A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/049921
申请日：2017-09-01
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WALKER, William L.
IPC分类号： G06F12/0811
摘要： A system (100) for managing cache utilization includes a processor core (111-114), one or more lower-level cache (131-134), and a higher-level cache (140). In response to activating the higher-level cache, the system counts (110) lower-level cache victims evicted from the lower-level cache. While a count of the lower-level cache victims is not greater than a threshold number, the system transfers each lower-level cache victim to a system memory (116) without storing the lower-level cache victim to the higher-level cache. When the count of the lower-level cache victims is greater than the threshold number, the system writes each lower-level cache victim to the higher-level cache. In this manner, if the higher-level cache is deactivated before the threshold number of lower-level cache victims is reached, the higher-level cache remains empty and thus may be deactivated without flushing.
摘要翻译：用于管理高速缓存利用的系统（100）包括处理器内核（111-114），一个或多个较低级别高速缓存（131-134）和较高级别高速缓存（140）。响应于激活较高级高速缓存，系统统计（110）从较低级高速缓存中逐出的较低级高速缓存受害者。尽管较低级别高速缓存受害者的计数不大于阈值数量，但是系统将每个较低级别高速缓存受害者传送到系统存储器（116）而不将较低级别高速缓存受害者存储到较高级别高速缓存。当较低级高速缓存受害者的计数大于阈值数时，系统将每个较低级高速缓存受害者写入较高级高速缓存。以这种方式，如果在达到较低级别高速缓存受害者的阈值数量之前停用较高级别的高速缓存，那么较高级别的高速缓存保持空着，因此可以在不刷新的情况下停用。

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