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1. 发明申请

WO2016046356A1 VORRICHTUNG ZUM DIGITALISIEREN EINES ANALOGEN SIGNALS 审中-公开
标题翻译：装置用于数字化模拟信号
公开(公告)号：WO2016046356A1
公开(公告)日：2016-03-31
申请号：PCT/EP2015/072075
申请日：2015-09-25
申请人： CONTINENTAL TEVES AG & CO. OHG
发明人： ACKER, Heinrich
IPC分类号： H03M1/20
CPC分类号： H03M1/0626 , H03M1/002 , H03M1/0614 , H03M1/1009 , H03M1/124 , H03M1/201 , H03M1/60
摘要： Die Erfindung betrifft eine Vorrichtung zum Digitalisieren eines analogen Signals, wobei ein Verzerrsignal-Ausgang eines Verzerrsignal-Generators ausschließlich mittels passiver Komponenten an einen Analog-Digital-Konverter gekoppelt ist.
摘要翻译：本发明涉及一种用于数字化模拟信号的装置，其中一个Verzerrsignal Verzerrsignal发生器的输出仅由无源元件的装置耦合到模拟数字转换器。

2. 发明申请

WO2012064498A2 VARIABLE DYNAMIC RANGE RECEIVER 审中-公开
标题翻译：可变动态范围接收器
公开(公告)号：WO2012064498A2
公开(公告)日：2012-05-18
申请号：PCT/US2011/057462
申请日：2011-10-24
申请人： ANALOG DEVICES, INC. , BRANNON, Joseph, Bradford , ROBERTSON, David, Hall , CAMP, James, C. , SPEIR, Carroll, C.
发明人： BRANNON, Joseph, Bradford , ROBERTSON, David, Hall , CAMP, James, C. , SPEIR, Carroll, C.
IPC分类号： H04L27/00 , H03M7/30
CPC分类号： H03M1/0614 , H03M1/12 , H03M1/66 , H04B1/001 , H04B1/0035
摘要： Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.
摘要翻译：本发明的实施例可以提供可包括模数转换器（ADC）和输出限制电路的信号处理电路。当信号内容超过不期望的频带中的预定频谱掩模时，输出限制电路可以降低ADC的数字输出的精度。在一个实施例中，可以主动地监视输入信号频谱，并且当输入频谱与预期应用不一致时，输出分辨率可被限制，例如通过截断数字输出的最低有效位（LSB）或添加数字噪声。

3. 发明申请

WO2010004455A3 A SWITCHED-CAPACITOR PIPELINE ADC STAGE 审中-公开
标题翻译：开关电容ADC管脚
公开(公告)号：WO2010004455A3
公开(公告)日：2010-02-25
申请号：PCT/IB2009052492
申请日：2009-06-11
申请人： NXP BV , BUTER BERRY ANTHONY JOHANNUS , VAN DE VAL HANS
发明人： BUTER BERRY ANTHONY JOHANNUS , VAN DE VAL HANS
IPC分类号： H03M1/12 , G11C27/02 , H03H19/00
CPC分类号： H03M1/0614 , G11C27/026 , H03M1/164 , H03M1/44
摘要： A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI)and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.
摘要翻译：公开了一种开关电容器流水线ADC级，其中包括复位开关以在采样周期的第一部分期间复位采样电容器。因此，复位开关从而消除历史，并使采样基本上与先前采样的采样无关，从而减少了由此产生的码间干扰（ISI）和失真，而不会显着影响设备的采样周期或功率使用。

4. 发明申请

WO2008042250A3 COMPOSITE ANALOG TO DIGITAL RECEIVER WITH ADAPTIVE SELF-LINEARIZATION 审中-公开
标题翻译：复合模拟到数字接收机的自适应自我线性化
公开(公告)号：WO2008042250A3
公开(公告)日：2008-07-24
申请号：PCT/US2007020915
申请日：2007-09-28
申请人： OPTICHRON INC
发明人： BATRUNI ROY G
IPC分类号： H03M1/06
CPC分类号： H03M1/0614 , H03M1/0626 , H03M1/1215
摘要： A distortion correcting analog to digital converter (ADC) system includes a plurality of ADCs configured to convert an analog signal to a plurality of digital ADC outputs, wherein the plurality of ADCs are configured to generate a composite signal based on the plurality of ADC outputs, there is an offset between a first one of the plurality of ADC outputs and a second one of the plurality of ADC outputs, the offset causing distortion in the composite signal. The system further includes an adaptive self-linearizer configured to receive the composite signal, and to perform self-linearization based on the composite signal to correct for the distortion in the composite signal. Generating a distortion corrected digital signal includes converting an analog signal to a plurality of digital signals; generating a composite signal based on the plurality of digital signals; wherein there is an offset between a first one of the plurality of ADC outputs and a second one of the plurality of ADC outputs, the offset causing distortion in the composite signal. The method further includes sending the composite signal to an adaptive self-linearizer and performing self-linearization based on the composite signal to correct for distortion in the composite signal.
摘要翻译：失真校正模数转换器（ADC）系统包括配置为将模拟信号转换为多个数字ADC输出的多个ADC，其中多个ADC被配置为基于多个ADC输出产生复合信号，在多个ADC输出中的第一个与多个ADC输出中的第二个之间存在偏移，该偏移在复合信号中引起失真。该系统进一步包括自适应自线性化器，其被配置为接收复合信号并且基于复合信号执行自线性化以校正复合信号中的失真。生成失真校正的数字信号包括将模拟信号转换为多个数字信号; 基于所述多个数字信号生成复合信号; 其中在所述多个ADC输出中的第一个与所述多个ADC输出中的第二个之间存在偏移，所述偏移在所述复合信号中引起失真。该方法进一步包括将复合信号发送到自适应自线性化器并且基于复合信号执行自线性化以校正复合信号中的失真。

5. 发明申请

WO2004075425A1 SYSTEMS AND METHODS FOR REDUCING HARMONIC INTERFERENCE EFFECTS IN ANALOG TO DIGITAL CONVERSION 审中-公开
标题翻译：用于减少模拟数字转换中谐波干扰效应的系统和方法
公开(公告)号：WO2004075425A1
公开(公告)日：2004-09-02
申请号：PCT/US2004/003884
申请日：2004-02-10
申请人： HONEYWELL INTERNATIONAL INC.
发明人： RICHEY, Manuel, F. , GIBSON, Timothy, P. , HUNTER, Jeffrey, K.
IPC分类号： H04B1/28
CPC分类号： H04B1/28 , H03M1/0614 , H03M1/12
摘要： Systems and methods are described for increasing the effective dynamic range of a digital data stream in a software-defined radio receiver. In one system the sample rate of an analog to digital ("A/D") conversion process is adjusted dynamically to shift harmonic signal interference induced by the A/D conversion process to outside the channels of interest. In another system the sample rate of an A/D conversion process is constant and the frequency of a dynamically controlled local oscillator in a frequency translator is adjusted dynamically to shift harmonic signal interference induced by the A/D conversion process to outside the channels of interest.
摘要翻译：描述了用于增加软件定义无线电接收机中的数字数据流的有效动态范围的系统和方法。在一个系统中，动态地调整模数（A / D）转换处理的采样速率，以将由A / D转换处理引起的谐波信号干扰移至感兴趣的信道之外。在另一个系统中，A / D转换过程的采样速率是恒定的，并且频率转换器中的动态控制的本地振荡器的频率被动态地调整，以将由A / D转换处理引起的谐波信号干扰移到感兴趣的信道之外。

6. 发明申请

WO2012064498A3 VARIABLE DYNAMIC RANGE RECEIVER 审中-公开
标题翻译：可变动态范围接收器
公开(公告)号：WO2012064498A3
公开(公告)日：2014-04-10
申请号：PCT/US2011057462
申请日：2011-10-24
申请人： ANALOG DEVICES INC , BRANNON JOSEPH BRADFORD , ROBERTSON DAVID HALL , CAMP JAMES C , SPEIR CARROLL C
发明人： BRANNON JOSEPH BRADFORD , ROBERTSON DAVID HALL , CAMP JAMES C , SPEIR CARROLL C
IPC分类号： H03M1/00
CPC分类号： H03M1/0614 , H03M1/12 , H03M1/66 , H04B1/001 , H04B1/0035
摘要： Embodiments of the present invention may provide a signal processing circuit that may comprises an analog-to-digital converter (ADC), and an output restriction circuit. The output restriction circuit may reduce the accuracy of the digital output of the ADC when signal content exceeds a pre-determined spectrum mask in an undesirable band. In one embodiment, the input signal spectrum may be actively monitored and when the input spectrum is inconsistent with an intended application, the output resolution may be restricted, for example, by truncating least significant bits (LSBs) of the digital output or adding digital noise.
摘要翻译：本发明的实施例可以提供可包括模数转换器（ADC）和输出限制电路的信号处理电路。当信号内容超过不期望的频带中的预定频谱掩模时，输出限制电路可以降低ADC的数字输出的精度。在一个实施例中，可以主动地监视输入信号频谱，并且当输入频谱与预期应用不一致时，输出分辨率可被限制，例如通过截断数字输出的最低有效位（LSB）或添加数字噪声。

7. 发明申请

WO2011114242A1 REDUCTION OF DIGITAL-TO-ANALOG CONVERTER DISTORTION USING CONSTELLATION ROTATION 审中-公开
标题翻译：使用协调旋转减少数字到模拟转换器的失真
公开(公告)号：WO2011114242A1
公开(公告)日：2011-09-22
申请号：PCT/IB2011/050592
申请日：2011-02-13
申请人： PROVIGENT LTD , FRIEDMANN, Jonathan , RAVID, Rafi
发明人： FRIEDMANN, Jonathan , RAVID, Rafi
IPC分类号： H03M1/66
CPC分类号： H03M1/0614 , H03M1/66 , H04L27/368
摘要： A method for signal conversion includes generating a complex digital signal, which includes digital In-phase (I) and Quadrature (Q) components, for conversion into respective analog I and Q components by first and second Digital-to-Analog Converters (DACs - 36A, 36B). A distortion generated by the DACS in the analog I and Q components is reduced by applying a phase rotation to the complex digital signal. After applying the phase rotation, the digital I and Q components of the complex digital signal are converted into the respective analog I and Q components using the first and second DACs.
摘要翻译：一种用于信号转换的方法包括生成包括数字同相（I）和正交（Q）分量的复数数字信号，用于由第一和第二数模转换器（DAC）转换成相应的模拟I和Q分量 36A，36B）。 DACS在模拟I和Q分量中产生的失真通过对复数数字信号施加相位旋转来减小。在施加相位旋转之后，使用第一和第二DAC将复数数字信号的数字I和Q分量转换成相应的模拟I和Q分量。

8. 发明申请

WO2009057110A3 METHOD AND APPARATUS FOR RECONSTRUCTING DIGITIZED DISTORTED SIGNALS 审中-公开
标题翻译：用于重构数字失真信号的方法和装置
公开(公告)号：WO2009057110A3
公开(公告)日：2010-03-11
申请号：PCT/IL2008001425
申请日：2008-10-29
申请人： TECHNION RES AND DEVELOPMENTFO , ELDAR YONINA , DVORKIND TSVI GREGORY
发明人： ELDAR YONINA , DVORKIND TSVI GREGORY
IPC分类号： G11B5/00
CPC分类号： H03M1/0614 , H03M1/12
摘要： A method of reproducing an original analog signal modified by a distortion and sampled. The distortion may be linear or nonlinear, and the samples may be either ideal or non-ideal. The method determines a stationary point of a cost function based on an error vector. The method iteratively computes approximated analog signals until the approximated analog signals converge to the original analog signal. The method may utilize Fr?chet derivatives and Moore-Penrose pseudo inverse transformations in order to iteratively compute the original analog signal. An apparatus performing said method is also disclosed.
摘要翻译：一种再现由失真和采样修正的原始模拟信号的方法。失真可以是线性的或非线性的，并且样本可以是理想的或非理想的。该方法基于误差向量确定成本函数的平稳点。该方法迭代地计算近似的模拟信号，直到近似的模拟信号收敛到原始模拟信号。该方法可以利用Fr？Chet导数和Moore-Penrose伪逆变换来迭代地计算原始模拟信号。还公开了执行所述方法的装置。

9. 发明申请

WO2010004455A2 A SWITCHED-CAPACITOR PIPELINE ADC STAGE 审中-公开
标题翻译：一个开关电容器管道ADC阶段
公开(公告)号：WO2010004455A2
公开(公告)日：2010-01-14
申请号：PCT/IB2009/052492
申请日：2009-06-11
申请人： NXP B.V. , BUTER, Berry Anthony Johannus , VAN DE VAL, Hans
发明人： BUTER, Berry Anthony Johannus , VAN DE VAL, Hans
IPC分类号： H03M1/12
CPC分类号： H03M1/0614 , G11C27/026 , H03M1/164 , H03M1/44
摘要： A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (ISI)and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.
摘要翻译：公开了一种开关电容器流水线ADC级，其中包括复位开关以在采样周期的第一部分期间复位采样电容器。因此复位开关去除了历史并且使得采样基本上独立于采用的先前采样，从而减少了由此导致的符号间干扰（ISI）和失真，而不显着影响设备的采样周期或功率使用。

10. 发明申请

WO2009030933A1 DIGITAL TO ANALOGUE CONVERTER CIRCUITS AND METHODS OF OPERATION THEREOF 审中-公开
标题翻译：数字到模拟转换器电路及其操作方法
公开(公告)号：WO2009030933A1
公开(公告)日：2009-03-12
申请号：PCT/GB2008/003030
申请日：2008-09-08
申请人： WOLFSON MICROELECTRONICS PLC , QUINN, Simon, Kenneth , HOWLETT, Andrew, James
发明人： QUINN, Simon, Kenneth , HOWLETT, Andrew, James
IPC分类号： H03M1/06 , H03M1/08 , H03M1/80 , H03M3/04
CPC分类号： H03M1/0614 , H03M1/0872 , H03M1/804 , H03M3/358 , H03M3/376 , H03M3/502
摘要： A multi-bit digital to analogue converter is implemented by a switched-capacitor arrangement in which a reservoir capacitor (Cf) accumulates charge representing the desired analogue output signal (Vout+/Vout-). An array of further capacitors (C0-CN) correspond in number at least to the number of data bits (D0-DN) to be converted. The capacitors (Cf, C0-CN) are selectively interconnected with one another and with reference voltage sources (Vmid, Vdd, Vss) in a repetitive sequence of phases including (i) a sampling phase (P2) in which said further capacitors are connected (S3, S4) to reference voltages selected in accordance with the values of said data bits, (ii) an equalisation phase (P6a) in which said further capacitors are connected (S2) in parallel with one another without connecting them in parallel with the first capacitor, followed by (iii) a transfer phase (P6b) in which the parallel connected further capacitors are connected (S1, S5) in parallel with the first capacitor. The equalisation phase masks nonlinearities arising in switches (S2) and thereby improves harmonic distortion.
摘要翻译：多位数模转换器由开关电容器布置实现，其中储存电容器（Cf）累积表示期望的模拟输出信号（Vout + / Vout-）的电荷。另外的电容器（C0-CN）的数组至少与要转换的数据位数（D0-DN）相对应。电容器（Cf，C0-CN）选择性地互相互连，并且以参考电压源（Vmid，Vdd，Vss）以相位重复的顺序相互连接，包括（i）其中所述另外的电容器被连接的采样相位（P2）（S3，S4），根据所述数据位的值选择参考电压，（ii）彼此并联连接所述另外的电容器（S2）的均衡相位（P6a），而不将它们与第一电容器，之后是（iii）与第一电容器并联连接有并联的另外的电容器（S1，S5）的转移相位（P6b）。均衡相屏蔽了开关（S2）中出现的非线性，从而改善了谐波失真。

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