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1. 发明申请

WO2012161003A1 DIVIDER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：使用相同的分路电路和半导体器件
公开(公告)号：WO2012161003A1
公开(公告)日：2012-11-29
申请号：PCT/JP2012/062245
申请日：2012-05-08
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , FUJITA, Masashi , MAEHASHI, Yukio
发明人： FUJITA, Masashi , MAEHASHI, Yukio
IPC分类号： H03K23/00 , H03K21/00 , H03K21/14 , H03K23/44
CPC分类号： H03K3/356156 , H03K21/023 , H03K23/44 , H03K23/52
摘要： A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
摘要翻译：提供具有低功耗和小面积的半导体器件。通过使用包括用于沟道的氧化物半导体的晶体管作为包括在触发器电路中的晶体管，可以实现晶体管数量少，功耗低，面积小的分压电路。通过使用分压电路，可以提供稳定运转且高可靠性的半导体装置。

2. 发明申请

WO2010038584A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2010038584A1
公开(公告)日：2010-04-08
申请号：PCT/JP2009/065617
申请日：2009-09-02
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , ATSUMI, Tomoaki
发明人： ATSUMI, Tomoaki
IPC分类号： H04B1/59 , G06K19/07 , H04B5/02 , H04L27/06
CPC分类号： H03K23/52 , H04L7/007 , H04L7/0331 , H04L7/04
摘要： It is an object of the present invention to provide a semiconductor device that has a simple circuit structure, a small scale, and low power consumption, and can generate a desired clock signal. The semiconductor device has a clock generation circuit which generates a clock signal by dividing a modulated carrier wave, a divider circuit which generates a first divided signal by dividing a carrier wave, and a correction circuit which generates a second divided signal by further dividing the first divided signal, and has a function of performing correction for inverting the second divided signal in a period corresponding to a half period of the clock signal during modulation of the carrier wave and selecting whether the correction is performed or not.
摘要翻译：本发明的目的是提供一种具有简单的电路结构，小规模和低功耗的半导体器件，并且可以产生期望的时钟信号。半导体器件具有时钟生成电路，其通过分压调制后的载波产生时钟信号，分频电路通过划分载波产生第一分频信号;校正电路，其通过进一步分割第一分频信号产生第二分频信号并且具有在对载波的调制期间对应于时钟信号的半周期的周期内执行用于反转第二分频信号的校正的功能，并且选择是否执行校正。

3. 发明申请

WO2016027329A1 分周回路及び半導体集積回路审中-公开
标题翻译：频率分段电路和半导体集成电路
公开(公告)号：WO2016027329A1
公开(公告)日：2016-02-25
申请号：PCT/JP2014/071766
申请日：2014-08-20
申请人：株式会社ソシオネクスト
发明人：田村　哲朗
IPC分类号： H03K27/00
CPC分类号： H03K23/52 , H03K3/037 , H03K3/0372 , H03K3/356026 , H03K19/21 , H03K21/026 , H03K21/12 , H03K23/54 , H03M9/00
摘要：　クロック信号の立ち上がり、立ち下がりで駆動されるラッチ回路を交互に接続し、複数のラッチ回路の出力のレベルの組み合わせを基に位相の異なる複数の分周クロック信号を生成することで、低消費電力の回路構成で正確なタイミングを有する分周クロック信号を生成することができるようにする。
摘要翻译：由时钟信号的上升和下降驱动的锁存电路被交替地连接，并且基于锁存电路的输出电平的组合产生具有不同相位的多个分频时钟信号，由此分频时钟可以在显示低功耗的电路装置中产生具有精确定时的信号。

4. 发明申请

WO2010035848A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：WO2010035848A1
公开(公告)日：2010-04-01
申请号：PCT/JP2009/066841
申请日：2009-09-17
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , ATSUMI, Tomoaki
发明人： ATSUMI, Tomoaki
IPC分类号： H01L21/82 , G06F17/50 , H01L21/822 , H01L27/04
CPC分类号： H03K23/52 , Y10T29/41
摘要： To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an inputted signal has a lower frequency in a following stage. Thus, placement is performed preferentially from the basic cell corresponding to the frequency-division circuit into which a signal having a higher frequency is inputted, and then wiring connection is performed. In other words, the layout of a plurality of basic cells corresponding to a multistage frequency-division circuit is performed so that, as compared to a wiring into which a signal having a lower frequency is inputted, a wiring into which a signal having a higher frequency is inputted has a shorter wiring length and has less intersection with other wirings, so that parasitic capacitance and parasitic resistance of the wiring are reduced.
摘要翻译：为了减少多级分频电路中的分频电路，特别是在多级分频电路中的电流消耗，输入信号在前级具有较高的频率，并且输入信号在后续阶段因此，优选地从对应于输入了具有较高频率的信号的分频电路的基本单元进行布置，然后进行布线连接。换句话说，执行与多级分频电路相对应的多个基本单元的布局，使得与输入具有较低频率的信号的布线相比，具有较高频率的信号的布线频率输入具有较短的布线长度，并且与其它布线的交点较少，因此布线的寄生电容和寄生电阻降低。

5. 发明申请

WO2005114841A1 APPARATUS AND METHOD FOR A PROGRAMMABLE CLOCK GENERATOR 审中-公开
标题翻译：可编程时钟发生器的装置和方法
公开(公告)号：WO2005114841A1
公开(公告)日：2005-12-01
申请号：PCT/US2005/015813
申请日：2005-05-06
申请人： HARRIS CORPORATION
发明人： BOURDEAU, Richard
IPC分类号： H03K21/00
CPC分类号： H03K23/52 , G06F1/0335
摘要： A gateless digital circuit and method for generating a second clock with a frequency of N/M of the frequency of a first clock, wherein N and M are integers, N≤ M/2. The gateless digital circuit having a modulo M function, a register and a adder operable connected to generate the second clock, where both N and M are independently selectable.
摘要翻译：一种用于产生频率为第一时钟的频率的N / M的第二时钟的无刷数字电路和方法，其中N和M是整数，N <= M / 2。无模数字电路具有模M功能，寄存器和加法器可操作连接以产生第二时钟，其中N和M都可独立选择。

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