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1. 发明申请

WO01089085A1 MATCHED FILTER 审中-公开
标题翻译：匹配过滤器
公开(公告)号：WO01089085A1
公开(公告)日：2001-11-22
申请号：PCT/JP2001/004032
申请日：2001-05-15
IPC分类号： H03H17/02 , H03H17/00 , G06F17/10 , H04J13/00
CPC分类号： H03H17/0254
摘要： A small-sized and power-saving matched filter circuit is provided. A succeeding stage of a matched filter includes a group of n hold circuits (H21, H22,..., H2n) to which the output signals (Dout1) from a preceding stage are coupled in parallel. The outputs of the hold circuits (H21 - H2n) are connected to multiplier circuits (M2l, M22, ..., M2n), respectively. The multiplier circuits multiply the outputs from the hold circuits (H21 - H2m) by multipliers (d21, d22,..., d2m). The outputs from the multiplier circuits (M21 - M2n) are supplied to a summing circuit (ADD2) to provide the sum (Dout2) (correlation output).
摘要翻译：提供了一种小型和省电的匹配滤波电路。匹配滤波器的后续级包括来自前一级的输出信号（Dout1）并行耦合的一组n个保持电路（H21，H22，...，H2n）。保持电路（H21-H2n）的输出分别连接到乘法电路（M2l，M22，...，M2n）。乘法器电路将乘法器（d21，d22，...，d2m）乘以保持电路（H21-H2m）的输出。来自乘法器电路（M21-M2n）的输出被提供给求和电路（ADD2）以提供和（Dout2）（相关输出）。

2. 发明申请

WO02078183A8 FILTER APPARATUS, RECEPTION APPARATUS, TRANSMISSION APPARATUS, DIFFUSION MODULATION APPARATUS, PSEUDO-RANDOM NUMBER SEQUENCE OUTPUT APPARATUS, FILTER METHOD, RECEPTION METHOD, TRANSMISSION METHOD, DIFFUSION MODULATION METHOD, PSEUDO-RANDOM NUMBER SEQUENCE OUTPUT METHOD, AND PROGRAM 审中-公开
标题翻译：滤波装置，接收装置，传输装置，扩散调制装置，PSEUDO随机数序列输出装置，滤波器方法，接收方法，传输方法，扩展调制方法，PSEUDO随机数序列输出方法和程序
公开(公告)号：WO02078183A8
公开(公告)日：2003-01-16
申请号：PCT/JP0202902
申请日：2002-03-26
申请人： JAPAN SCIENCE & TECH CORP , UMENO KEN , SHIH SHENGHUNG , YAMAGUCHI AKIHIRO
发明人： UMENO KEN , SHIH SHENGHUNG , YAMAGUCHI AKIHIRO
IPC分类号： H03H17/02 , H03H17/06 , H04B1/707 , H04J13/04
CPC分类号： H04J13/0018 , H03H17/0254 , H04B1/7093 , H04J13/10
摘要： A filter (201) accepts a diffusion code sequence or the like as an input sequence at the chip late 1/D. The diffusion code sequences accepted are successively delayed by a delay circuit (202) connected in series, and delivered. Delay times of the signals constitute an arithmetic progression having a common difference of the chip length D. Diffusion codes of the signals are amplified by an amplifier (203), so that the amplification ratio constitutes a geometric progression having a common ratio r. A total of the amplified signals is calculated by addition by an adder (204) and the addition result is successively output as an output sequence.
摘要翻译：过滤器（201）接受扩散码序列等作为码片1 / D处的码片输入序列。接受的扩散码序列被连续串联的延迟电路（202）连续地延迟并传送。信号的延迟时间构成具有芯片长度D的共同差的算术级数。信号的扩散码由放大器（203）放大，使得放大率构成具有公共比率r的几何级数。通过加法器（204）的加法来计算总共放大的信号，并且相加输出作为输出序列输出。

3. 发明申请

WO01028091A1 DIGITAL FILTER COMBINATION 审中-公开
标题翻译：数字滤波器组合
公开(公告)号：WO01028091A1
公开(公告)日：2001-04-19
申请号：PCT/EP2000/010015
申请日：2000-10-11
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0286 , H03H17/0254 , H03H17/0621
摘要： Receiver systems often use filter combinations of resampling filters and matched filters to decimate the input signal and to adapt it to the pulse form of the sender signal. Due to the independent functions these two filters fulfil, they are designed independently of one another. According to the invention, the transmission band of the resampling filter and the matched filter is chosen so as to produce a smooth amplitude response curve when these filters are combined. The inventive filter combination is used in digital receiver systems.
摘要翻译：在接收重采样滤波器和匹配滤波器的系统过滤器组合通常用于所述输入信号的抽取和它适应所述发射机信号的脉冲形状。由于独立的任务两个过滤器是分开设计的。根据本发明，在每种情况下选择重新采样滤波器的通带和匹配滤波器，使得光滑的振幅响应从这些滤波器的组合的结果。在数字接收系统中使用的发现本发明的滤波器组合。

4. 发明申请

WO2003077441A1 DIGITAL CORRELATORS 审中-公开
标题翻译：数码相机
公开(公告)号：WO2003077441A1
公开(公告)日：2003-09-18
申请号：PCT/JP2003/002937
申请日：2003-03-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： LEWIS, Jonathan David
IPC分类号： H04B1/707
CPC分类号： H04B1/7093 , G06F17/15 , H03H17/0254 , H04B1/7095
摘要： The invention generally relates to improved correlators for spread spectrum receivers, particularly for third generation (3G) mobile communications systems. A Golay correlator with a plurality of delay structures is described. At least one of these delay structures comprises a plurality of memory elements (704) sharing a common input bus (720), and a circular shift register (610) having a plurality of bit positions (712), one for each of the memory elements, each bit position storing a single bit and having an associated bit position output (706), each bit position output being coupled to a corresponding one of the memory elements for enabling writing of data into the memory element when the bit position output is active, and wherein, in use, only one of the bit positions in the circular shift register is active, the active bit position moving circularly through the shift register to select the memory element into which data on the common bus is written. The circular shift register may be shared between two or more of the delay structures.
摘要翻译：本发明一般涉及用于扩频接收机的改进的相关器，特别是对于第三代（3G）移动通信系统。描述了具有多个延迟结构的Golay相关器。这些延迟结构中的至少一个包括共享公共输入总线（720）的多个存储器元件（704）和具有多个位位置（712）的圆形移位寄存器（610），每个存储器元件每个位位置存储单个位并且具有相关联的位位置输出（706），每个位位置输出耦合到存储器元件中的相应一个，用于当位位置输出有效时将数据写入存储元件，并且其中，在使用中，循环移位寄存器中只有一个位位置有效，活动位位置循环移动通过移位寄存器，以选择写入公共总线上的数据的存储元件。循环移位寄存器可以在两个或更多个延迟结构之间共享。

5. 发明申请

WO00028662A1 DIGITAL FILTER WITH PARALLEL ARCHITECTURE AND SPREAD-SPECTRUM SIGNAL RECEIVER USING SAME 审中-公开
标题翻译：具有平行架构和扩频信号接收器的数字滤波器
公开(公告)号：WO00028662A1
公开(公告)日：2000-05-18
申请号：PCT/FR1999/002724
申请日：1999-11-08
IPC分类号： H03H17/02 , H03H17/06 , H04J13/00
CPC分类号： H03H17/06 , H03H17/0254 , H04J13/0022
摘要： The invention concerns a digital filter with parallel architecture and a spread-spectrum signal receiver using such a filter. The filter comprises p shift registers (R , R ) with means for working out a weighted sum of the samples stored in the registers, thereby obtaining p weighted sums (S k, S k) which can be recombined. The number p can be equal to 2. The invention is applicable to digital transmissions with spread-spectrum.
摘要翻译：本发明涉及具有并行架构的数字滤波器和使用这种滤波器的扩频信号接收机。滤波器包括具有用于计算存储在寄存器中的样本的加权和的装置的p个移位寄存器（R p，R i），从而获得p个加权和（S k，S k ）可以重新组合。数字p可以等于2.本发明适用于具有扩频的数字传输。

6. 发明申请

WO01028120A1 RING MATCHED FILTER FOR SYNCHRONIZING TO A SPREADING CODE 审中-公开
标题翻译：环形匹配过滤器，用于同步传播代码
公开(公告)号：WO01028120A1
公开(公告)日：2001-04-19
申请号：PCT/IB2000/001456
申请日：2000-10-09
IPC分类号： H03H17/02 , H04B1/7093 , H04B1/707
CPC分类号： H04B1/7093 , H03H17/0254
摘要： A mobile station is provided for receiving a spread spectrum, code division transmission from at least one transmitter, such as a base station. The mobile station contains a receiver for outputting data samples, and further contains a multi-tap ring matched filter. The ring matched filter is constructed to have first circuitry for storing an individual one of a received data sample into an individual one of a plurality storage registers such that an active data sample that has been stored for the longest period of time is overwritten with a most recently received data sample. The ring matched filter is further constructed to have second circuitry for serially shifting coefficient bits of at least one multi-bit spreading code relative to the storage registers for sequentially and simultaneously correlating the at least one multi-bit spreading code with a plurality of corresponding stored data samples, while significantly reducing power consumption by limiting state changes of flip-flops.
摘要翻译：移动台被提供用于从诸如基站的至少一个发射机接收扩频，码分多址传输。移动站包含用于输出数据采样的接收机，并且还包含多抽头环匹配滤波器。环形匹配滤波器被构造成具有第一电路，用于将接收到的数据样本中的单独一个存储到多个存储寄存器中的单独一个中，使得已经存储了最长时间段的活动数据样本被最多地覆盖最近收到的数据样本。环形匹配滤波器还被构造成具有用于相对于存储寄存器串行地移位至少一个多位扩展码的系数比特的第二电路，用于顺序地并且同时地将至少一个多比特扩展码与多个对应的存储数据样本，同时通过限制触发器的状态变化显着降低功耗。

7. 发明申请

WO01003293A1 MATCHED FILTER USING TIME-MULTIPLEXED PRECOMBINATIONS 审中-公开
标题翻译：使用时间多重预处理的匹配滤波器
公开(公告)号：WO01003293A1
公开(公告)日：2001-01-11
申请号：PCT/US2000/015508
申请日：2000-06-07
IPC分类号： G06F17/15 , H03H17/02 , H04B1/7075 , H04B1/7093
CPC分类号： G06F17/15 , H03H17/0254 , H04B1/70751 , H04B1/70752 , H04B1/7093 , H04B2201/70707
摘要： A technique for correlating a stream of signal sample values with a predetermined binary code having a plurality of binary code bits is disclosed. The technique is realized by forming precombinations of groups of the signal sample values in the stream, and then temporally ordering the precombinations. Particular ones of the temporally ordered precombinations are selected based upon particular combinations of the plurality of binary code bits. The particular selected ones of the temporally ordered precombinations are then combined to form a correlation.
摘要翻译：公开了一种用于将信号采样值流与具有多个二进制码位的预定二进制码进行相关的技术。该技术通过在流中形成信号样本值的组的预组合，然后在时间上排序预组合来实现。基于多个二进制码位的特定组合来选择时间有序的预组合中的特定的组合。然后将时间有序的预组合中的特定选定的组合形成相关性。

8. 发明申请

WO00060738A1 COMPLEX MATCHED FILTER WITH REDUCED POWER CONSUMPTION 审中-公开
标题翻译：具有降低功耗的复合匹配滤波器
公开(公告)号：WO00060738A1
公开(公告)日：2000-10-12
申请号：PCT/US2000/008985
申请日：2000-04-03
IPC分类号： H03H17/06 , H03H17/02 , H04J13/00
CPC分类号： H03H17/0202 , H03H17/0254
摘要： A matched filter computes complex correlations between a sequence of complex input values and a complex code. The matched filter includes a set of N changeover switches (55) having a first input connected to receive real parts (Sr) of the input sample values and a second input connected to receive imaginary parts (Si) of the input sample values. The switches (55) further include a control input for receiving a control signal (CN) in first and second states. When the control signal (CN) in the first state is applied, a first output of the changeover switch (55) contains the real value part (Sr) of the input sample values and a second input contains the imaginary part (Si) of the input sample values. When the control signal (CN) is in the second state the first input contains the imaginary value part (Si) of the input sample values and the second input contains the real value part (Sr) of the input sample values.
摘要翻译：匹配滤波器计算复杂输入值序列与复杂代码之间的复杂相关性。匹配滤波器包括一组N个转换开关（55），其具有连接以接收输入采样值的实部（Sr）的第一输入端和连接成接收输入采样值的虚部（Si）的第二输入端。开关（55）还包括用于在第一和第二状态下接收控制信号（CN）的控制输入端。当施加处于第一状态的控制信号（CN）时，转换开关（55）的第一输出包含输入采样值的实数值部分（Sr），第二输入端包含第输入样本值。当控制信号（CN）处于第二状态时，第一输入包含输入采样值的虚数部分（Si），第二输入包含输入采样值的实值部分（Sr）。

9. 发明申请

WO00054142A2 DEVICE FOR COMPARING DATA SEQUENCES 审中-公开
标题翻译：设备比较数据都遵循
公开(公告)号：WO00054142A2
公开(公告)日：2000-09-14
申请号：PCT/DE1999/000622
申请日：1999-03-09
IPC分类号： H03H17/02 , G06F7/00
CPC分类号： H03H17/0254
摘要： The invention relates to a device for comparing data sequences. The device can be used especially for determining the channel impulse response in mobile radiotelephone systems by comparing a receive sequence (r(t)) with a pilot sequence (s(t)). The individual values of the output data sequence (m(t)) that is received as the result of the comparison are generated in parallel by means of an appropriate arrangement of delay elements (1), combination circuits (5) and feedback adders (3).
摘要翻译：它提出了一种装置，用于比较，可以特别用于确定在移动无线电系统的信道脉冲响应的数据序列，通过提供一种接收序列（R（T）），与导频序列（S（t））的相比较。作为比较结果的输出数据序列（M（t））的所获得的单独的值都在由平行的延迟元件（1）的相应阵列中，组合电路（5）生成并反馈的加法器（3）。

10. 发明申请

WO99006922A1 DIGITAL MATCHED FILTER 审中-公开
标题翻译：数字匹配滤波器
公开(公告)号：WO99006922A1
公开(公告)日：1999-02-11
申请号：PCT/JP1997/002647
申请日：1997-07-30
IPC分类号： H03H17/02 , H04B1/7093 , H04J13/00 , G06F17/15 , H04J13/02
CPC分类号： H04B1/7093 , H03H17/0254
摘要： The power consumption of a digital matched filter for finding the value of the correlation between 6-bit digital signals (I0) synchronized with a clock and an inverse spectrum spread code sequence composed of eight inverse spectrum spread codes (C7, C6, C5, C4, C3, C2, C1, and C0) is reduced. First to eighth flip-flops (211-218) constituting a storing section (210) are successively selected one by one at a clock by means of a write selecting circuit (220), and the digital signals (I0) are stored in the selected flip-flops. The eight inverse spectrum spread codes are respectively stored in first to eight flip-flops (231-238) for code storage and shifted synchronously with the clock. The output signals of the first to eighth flip-flop are respectively multiplied by the output signals of the first to eighth flip-flops (231-238) for code storage by means of first to eight multiplying circuits (241-248).
摘要翻译：用于找出与时钟同步的6位数字信号（I0）与由8个反向频谱扩展码（C7，C6，C5，C4）组成的逆频谱扩展码序列之间的相关值的数字匹配滤波器的功耗，C3，C2，C1和C0）。构成存储部分（210）的第一至第八触发器（211-218）通过写入选择电路（220）在时钟上依次逐个选择，数字信号（I0）存储在所选择的人字拖。八个反向频谱扩展码分别存储在第一至八个触发器（231-238）中用于代码存储并与时钟同步地移位。第一至第八触发器的输出信号分别乘以第一至第八触发器（231-238）的输出信号，以通过第一至第八乘法电路（241-248）进行代码存储。

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