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1. 发明申请

WO2016002508A1 半導体集積回路装置审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：WO2016002508A1
公开(公告)日：2016-01-07
申请号：PCT/JP2015/067370
申请日：2015-06-16
申请人：富士電機株式会社
发明人：山路　将晴
IPC分类号： H01L27/08 , H01L21/76 , H01L21/822 , H01L21/8234 , H01L27/04 , H01L27/088 , H02M3/155 , H02M7/48
CPC分类号： H03K19/018521 , H01L21/76 , H01L21/823892 , H01L27/082 , H01L27/092 , H01L27/0922 , H01L29/0649 , H01L29/1095 , H01L29/7393 , H01L29/861 , H02M7/003 , H03K17/567
摘要：　ｎ型ウエル領域（３）には、Ｖｓ電位領域（８１）およびＨ－ＶＤＤ電位領域（８２）が配置され、外周に沿って環状に、ｎ型ウエル領域（３）内のＶｓ電位領域（８１）およびＨ－ＶＤＤ電位領域（８２）と、耐圧領域であるｎ - 型ウエル領域（４）とを接合分離するｐ - 型分離領域（５３）が配置されている。ｎ - 型ウエル領域（４）は、ｎ型ウエル領域（３）の周囲を囲み、ＧＮＤの電位に固定されたｐ型ウエル領域（５）に囲まれている。ｐ - 型分離領域（５３）よりも内側に、Ｈ－ＶＤＤの電位に固定された第３高濃度領域（５４）および第３ピックアップ電極（５５）が配置される。ｐ - 型分離領域（５３）よりも外側に、ｐ - 型分離領域（５３）の外周に沿って、Ｈ－ＶＤＤの電位に固定された第２高濃度領域（５１）および第２ピックアップ電極（５２）が配置される。このようにすることで、半導体集積回路装置の誤動作や破壊を防止することができる。
摘要翻译：在n型阱区（3）内布置有Vs电势区（81）和H-VDD势区（82），以及在Vs电位之间实现结隔离的p型隔离区（53） n型阱区域（3）内的区域（81）和H-VDD电势区域（82）以及充当电压耐受区域的n型阱区域（4）沿着 n型阱区（3）形成环。 n型阱区（4）包围n型阱区（3），并被固定在接地电位的p型阱区（5）环绕。固定在H-VDD电位的第三拾取电极（55）和第三高浓度区域（54）布置在p型隔离区域（53）的内侧，第二拾取电极（52）和第二高电平也固定在H-VDD电位的浓度区域（51）沿着其周边布置在p型隔离区域（53）的外侧。这使得可以防止半导体集成电路装置发生故障或遭受损坏。

2. 发明申请

WO00019535A1 SEMICONDUCTOR STRUCTURE FOR SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体元件的半导体结构
公开(公告)号：WO00019535A1
公开(公告)日：2000-04-06
申请号：PCT/EP1999/007226
申请日：1999-09-29
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a semiconductor structure for producing semiconductor components, for example PNP transistors. The inventive semiconductor structure has a trough-shaped n-doped area (5) in a p-doped semiconductor material (1, 2), said trough encompassing a p-doped inner area (6) which extends as far as the surface of the semiconductor material. The trough-shaped n-doped area (5) is much more strongly doped that the p-doped inner area (6). The semiconductor structure is technologically simple to produce and is compatible with modern CMOS processes. The structure forms an output structure, especially for a vertical PNP transistor, with improved electrical properties, for example current amplification and frequency characteristics.
摘要翻译：用于半导体器件，例如PNP晶体管的制造中的半导体结构具有在p型掺杂的半导体材料的槽形n掺杂区（5）（1，2）（一个在到达p型掺杂的内部区6中的半导体材料的表面）包围。槽形n掺杂区（5）具有比p掺杂内区（6）的掺杂强得多的掺杂。半导体结构在技术上容易制造并且与现代CMOS工艺兼容。它形成了一个输出结构，特别是对于具有改进的电性能（例如电流增益和频率响应）的垂直PNP晶体管。

3. 发明申请

WO2009107993A2 HIGH CURRENT CONTROL CIRCUIT INCLUDING METAL-INSULATOR TRANSITION DEVICE, AND SYSTEM INCLUDING THE HIGH CURRENT CONTROL CIRCUIT 审中-公开
标题翻译：包括金属绝缘子过渡装置的高电流控制电路和包括高电流控制电路的系统
公开(公告)号：WO2009107993A2
公开(公告)日：2009-09-03
申请号：PCT/KR2009/000932
申请日：2009-02-27
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , Kim, Hyun-Tak , KIM, Bong-Jun , YUN, Sun-Jin
发明人： Kim, Hyun-Tak , KIM, Bong-Jun , YUN, Sun-Jin
IPC分类号： H01L49/00 , H01L29/73 , H01L29/772
CPC分类号： H01L21/8222 , H01L23/62 , H01L27/067 , H01L27/082 , H01L2924/0002 , H03K17/14 , H03K17/567 , H01L2924/00
摘要： Provided are a high current control circuit including a metal-insulator transition (MIT) device, and a system including the high current control circuit so that a high current can be controlled and switched by the small-size high current control circuit, and a heat generation problem can be solved. The high current control circuit includes the MIT device connected to a current driving device and undergoing an abrupt MIT at a predetermined transition voltage; and a switching control transistor connected between the current driving device and the MIT device and controlling on-off switching of the MIT device. By including the metal-insulator transition (MIT) device, the high current control circuit switches a high current that is input to or output from the current driving device. Also, the MIT device constitutes a MIT-TR composite device with a heat-preventing transistor which prevents heat generation and is connected to the MIT device.
摘要翻译：提供了包括金属 - 绝缘体转变（MIT）器件的高电流控制电路和包括高电流控制电路的系统，使得可以通过小尺寸高电流控制电路来控制和切换高电流，并且提供热量生成问题可以解决。高电流控制电路包括连接到电流驱动装置的MIT装置，并且在预定转换电压下经历突发MIT; 以及连接在电流驱动装置和MIT装置之间的开关控制晶体管，并且控制MIT装置的开 - 关切换。通过包括金属 - 绝缘体转变（MIT）器件，高电流控制电路切换输入到当前驱动装置或从当前驱动装置输出的高电流。此外，MIT装置构成具有防止发热并与MIT装置连接的防热晶体管的MIT-TR复合装置。

4. 发明申请

WO1993006622A1 COMPLEMENTARY BIPOLAR TRANSISTORS HAVING HIGH EARLY VOLTAGE, HIGH FREQUENCY PERFORMANCE AND HIGH BREAKDOWN VOLTAGE CHARACTERISTICS AND METHOD OF MAKING SAME 审中-公开
标题翻译：具有高电压，高频性能和高突变电压特性的补偿双极晶体管及其制造方法
公开(公告)号：WO1993006622A1
公开(公告)日：1993-04-01
申请号：PCT/US1992008211
申请日：1992-09-25
申请人： HARRIS CORPORATION
发明人： HARRIS CORPORATION , DAVIS, Christopher, K. , BAJOR, George , CRANDELL, Thomas, L. , JUNG, Taewon , RIVOLI, Anthony, L. , BEASOM, James, D.
IPC分类号： H01L29/73
CPC分类号： H01L29/66272 , H01L21/8228 , H01L21/82285 , H01L21/84 , H01L27/0623 , H01L27/082 , H01L27/0826 , H01L27/1203 , H01L29/0821 , H01L29/167 , H01L29/7325 , H01L29/808 , H01L29/8605
摘要： Complementary bipolar transistors and a process for fabrication on a dielectrically isolated substrate. Both the NPNs and PNPs have an emitter (74, 80) diffused from an emitter polysilicon contact (68A, 68B) and an extrinsic base (52, 56) diffused from a base polysilicon contact (40, 42) with the emitter polysilicon contact separated from the base polysilicon contact by sidewall oxide/nitride. This provides shallow emitters and a small emitter-to-extrinsic base distance and high performance.
摘要翻译：互补双极晶体管和用于在介电隔离衬底上制造的工艺。 NPN和PNP都具有从发射极多晶硅接触（68A，68B）扩散的发射极（74,80）和从基极多晶硅接触（40,42）扩散的外部基极（52,56），发射极多晶硅接触分离通过侧壁氧化物/氮化物从基底多晶硅接触。这提供了浅发射器和小的发射极到非本征基极距离和高性能。

5. 发明申请

WO2013032906A1 PARALLEL CONNECTION METHODS FOR HIGH PERFORMANCE TRANSISTORS 审中-公开
标题翻译：高性能晶体管的并联连接方法
公开(公告)号：WO2013032906A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052271
申请日：2012-08-24
申请人： EFFICIENT POWER CONVERSION CORPORATION , DE ROOIJ, Michael, A. , STRYDOM, Johan
发明人： DE ROOIJ, Michael, A. , STRYDOM, Johan
IPC分类号： H03K17/56
CPC分类号： H01L27/0207 , H01L27/082 , H01L27/085 , H03K17/122
摘要： Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.
摘要翻译：并联晶体管电路具有从普通源极感应效应降低的效果。并联晶体管包括物理栅极连接，这些物理栅极连接彼此电气靠近。并联电路被布置成使得由跨过公共源电感的瞬态电流产生的公共栅极连接处的电压基本上是平衡的。电路包括开关电路，转换器和RF放大器。

6. 发明申请

WO98036453A1 ANTIFUSE BASED ON SILICIDED POLYSILICON BIPOLAR TRANSISTOR 审中-公开
标题翻译：基于硅的多晶硅双极晶体管的抗体
公开(公告)号：WO98036453A1
公开(公告)日：1998-08-20
申请号：PCT/CA1998/000114
申请日：1998-02-13
IPC分类号： H01L23/525 , H01L27/082 , H01L27/102
CPC分类号： H01L23/5252 , H01L27/082 , H01L27/1022 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor (40). The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament (146) formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse. A similar technique may be used with a double polysilicon bipolar transistor (110).
摘要翻译：一种改进的反熔丝，其采用硅化单晶硅双极晶体管（40）的基极 - 发射极结。贱金属和发射极之间的距离缩短，并由自对准工艺步骤而不是光刻步骤产生，从而导致编程电压更低和更好，编程能量和导通状态电阻。通常，形成在新反熔丝中的导电细丝（146）的长度约为0.65微米，并且由具有相对较慢的上升时间（例如150微秒）的电压脉冲形成，从而提供了改进的性质，其在电路设计和制造电路中提供优点使用新的反熔丝。类似的技术可以与双重多晶硅双极晶体管（110）一起使用。

7. 发明申请

WO2012173693A1 COMPLEMENTARY BIPOLAR INVERTER 审中-公开
标题翻译：补充双极反相器
公开(公告)号：WO2012173693A1
公开(公告)日：2012-12-20
申请号：PCT/US2012/033713
申请日：2012-04-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CAI, Jin , DENNARD, Robert H. , HAENSCH, Wilfried E. , NING, Tak H.
发明人： CAI, Jin , DENNARD, Robert H. , HAENSCH, Wilfried E. , NING, Tak H.
IPC分类号： H01L21/70
CPC分类号： H01L27/1203 , H01L21/8228 , H01L21/84 , H01L27/082
摘要： An example embodiment is a complementary transistor inverter circuit. The circuit includes a semiconductor-on-insulator (SOI) substrate, a lateral PNP bipolar transistor fabricated on the SOI substrate, and a lateral NPN bipolar transistor fabricated on the SOI substrate. The lateral PNP bipolar transistor includes a PNP base, a PNP emitter, and a PNP collector. The lateral NPN bipolar transistor includes a NPN base, a NPN emitter, and a NPN collector. The PNP base, the PNP emitter, the PNP collector, the NPN base, the NPN emitter, and the NPN collector abut the buried insulator of the SOI substrate.
摘要翻译：示例性实施例是互补晶体管反相器电路。电路包括绝缘体上半导体（SOI）衬底，制造在SOI衬底上的横向PNP双极晶体管，以及制造在SOI衬底上的横向NPN双极晶体管。横向PNP双极晶体管包括PNP基极，PNP发射极和PNP集电极。横向NPN双极晶体管包括NPN基极，NPN发射极和NPN集电极。 PNP基极，PNP发射极，PNP集电极，NPN基极，NPN发射极和NPN集电极邻接SOI衬底的埋层绝缘体。

8. 发明申请

WO2009096940A1 COMMON BASE LATERAL BIPOLAR JUNCTION TRANSISTOR CIRCUIT FOR AN INKJET PRINT HEAD 审中-公开
标题翻译：用于喷墨打印头的通用基板侧向双极性连接晶体管电路
公开(公告)号：WO2009096940A1
公开(公告)日：2009-08-06
申请号：PCT/US2008/052164
申请日：2008-01-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , GUPTA, Rohit , GHOZEIL, Adam , PEH, Bee
发明人： GUPTA, Rohit , GHOZEIL, Adam , PEH, Bee
IPC分类号： B41J2/14 , B41J2/145 , B41J2/05
CPC分类号： B41J2/14072 , B41J2/04541 , B41J2/04543 , B41J2/04563 , B41J2/0458 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2202/13 , H01L27/082
摘要： A print head circuit of an inkjet printer comprising a plurality of row heating elements arranged in a plurality of rows, a plurality of column heating elements arranged in a plurality of columns, and a plurality of lateral bipolar junction transistors (BJTs), each lateral BJT is connected in between and in series with a corresponding one of the plurality of row heating elements and a corresponding one of the plurality of column heating elements, the plurality of lateral BJTs have common bases, wherein the plurality of row heating elements and the plurality of column heating elements are selectively energized to heat ink in the inkjet printer in a desired pattern for printing media, and wherein each of the plurality of lateral BJTs operates to allow the corresponding row and column heating elements that are connected in series with the lateral BJT to be energized.
摘要翻译：一种喷墨打印机的打印头电路，包括排列成多排的多个行加热元件，多个列排列的多个列加热元件和多个横向双极结型晶体管（BJT），每个侧向BJT 与所述多个行加热元件中的相应一个和所述多个列加热元件中的相应一个连接在一起，并且与所述多个列加热元件中的相应一个连接，所述多个横向BJT具有公共基座，其中所述多个行加热元件和所述多个行加热元件列加热元件被选择性地通电以以所需的印刷媒体图案加热喷墨打印机中的墨，并且其中多个横向BJT中的每一个操作以允许与横向BJT串联连接的相应的行和列加热元件通电。

9. 发明申请

WO00019503A1 METHOD FOR PRODUCING TRANSISTORS 审中-公开
标题翻译：用于生产TRANSISTORS
公开(公告)号：WO00019503A1
公开(公告)日：2000-04-06
申请号：PCT/EP1999/005942
申请日：1999-08-13
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10 , H01L21/266 , H01L21/74 , H01L21/761 , H01L31/11
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation, using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species, i.e., n is exchanged for p and vice versa.
摘要翻译：本发明涉及用于积半导体部件，尤其是晶体管或逻辑门，由p型掺杂的半导体衬底开始的制备方法。在半导体基板的掩模用于限定由所述窗口的周界边缘首先被施加。接着，在半导体衬底中阱的n掺杂通过离子注入用的能量足够了p掺杂的内部区域保持所述半导体衬底的表面上，其中，所述的边缘区域n掺杂阱延伸到半导体衬底的表面上产生。另，形成晶体管或逻辑门n掺杂和/或然后p掺杂区被引入到半导体衬底的p型掺杂的内区的结构。以考虑为昂贵的外延和隔离工艺的方法是有利的。在n型掺杂的半导体衬底的所有注入由互补的物种所取代，即，n与p，反之亦然。

10. 发明申请

WO2015143216A1 HV COMPLEMENTARY BIPOLAR TRANSISTORS WITH LATERAL COLLECTORS ON SOI 审中-公开
标题翻译：在SOI上具有横向收集器的高压互补双极晶体管
公开(公告)号：WO2015143216A1
公开(公告)日：2015-09-24
申请号：PCT/US2015/021566
申请日：2015-03-19
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SADOVNIKOV, Alexei , BABCOCK, Jeffrey A.
IPC分类号： H01L27/102
CPC分类号： H01L27/1203 , H01L23/535 , H01L27/082 , H01L29/063 , H01L29/0634 , H01L29/0649 , H01L29/0692 , H01L29/0808 , H01L29/0821 , H01L29/10 , H01L29/1008 , H01L29/66265 , H01L29/66272 , H01L29/732 , H01L29/735
摘要： In described examples of complementary high- voltage bipolar transistors (100) in silicon-on-insulator (SOI) integrated circuit, a collector region (104) is formed in an epitaxial silicon layer disposed over a buried insulator layer BOX (103). A base region (113) and an emitter (108) are disposed over the collector region (104). An n-type region (106) is formed under the BOX (103) by implanting donor impurity through the active region of substrate and BOX (103) into a p-substrate (101). Later in the process flow, this n-type region (106) is connected from the top by doped polysilicon plug (110) and is biased at Vcc. In this case, it will deplete lateral portion of PNP collector region and will increase its BV.
摘要翻译：在绝缘体上硅（SOI）集成电路中的互补高电压双极晶体管（100）的所述实例中，集电极区（104）形成在设置在掩埋绝缘体层BOX（103）上的外延硅层中。基极区域（113）和发射极（108）设置在集电极区域（104）上方。通过将施主杂质通过衬底和BOX（103）的有源区域注入到p衬底（101）中，在BOX（103）下方形成n型区域（106）。在该工艺流程中，该n型区域（106）从顶部通过掺杂多晶硅插塞（110）连接并被偏置在Vcc。在这种情况下，会消耗PNP集电极区域的侧面部分，并增加其BV。

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