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1. 发明申请

WO00019503A1 METHOD FOR PRODUCING TRANSISTORS 审中-公开
标题翻译：用于生产TRANSISTORS
公开(公告)号：WO00019503A1
公开(公告)日：2000-04-06
申请号：PCT/EP1999/005942
申请日：1999-08-13
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10 , H01L21/266 , H01L21/74 , H01L21/761 , H01L31/11
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation, using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species, i.e., n is exchanged for p and vice versa.
摘要翻译：本发明涉及用于积半导体部件，尤其是晶体管或逻辑门，由p型掺杂的半导体衬底开始的制备方法。在半导体基板的掩模用于限定由所述窗口的周界边缘首先被施加。接着，在半导体衬底中阱的n掺杂通过离子注入用的能量足够了p掺杂的内部区域保持所述半导体衬底的表面上，其中，所述的边缘区域n掺杂阱延伸到半导体衬底的表面上产生。另，形成晶体管或逻辑门n掺杂和/或然后p掺杂区被引入到半导体衬底的p型掺杂的内区的结构。以考虑为昂贵的外延和隔离工艺的方法是有利的。在n型掺杂的半导体衬底的所有注入由互补的物种所取代，即，n与p，反之亦然。

2. 发明申请

WO0019535B1 SEMICONDUCTOR STRUCTURE FOR SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体结构半导体器件
公开(公告)号：WO0019535B1
公开(公告)日：2000-05-11
申请号：PCT/EP9907226
申请日：1999-09-29
申请人： GRUETZEDIEK URSULA , SCHEERER JUTTA , GRUETZEDIEK HARTMUT , SCHEERER JOACHIM
发明人： GRUETZEDIEK HARTMUT , SCHEERER JOACHIM
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a semiconductor structure for producing semiconductor components, for example PNP transistors. The inventive semiconductor structure has a trough-shaped n-doped area (5) in a p-doped semiconductor material (1, 2), said trough encompassing a p-doped inner area (6) which extends as far as the surface of the semiconductor material. The trough-shaped n-doped area (5) is much more strongly doped that the p-doped inner area (6). The semiconductor structure is technologically simple to produce and is compatible with modern CMOS processes. The structure forms an output structure, especially for a vertical PNP transistor, with improved electrical properties, for example current amplification and frequency characteristics.
摘要翻译：用于半导体器件，例如PNP晶体管的制造中的半导体结构具有在p型掺杂的半导体材料的槽形n掺杂区（5）（1，2）（一个在到达p型掺杂的内部区6中的半导体材料的表面）包围。槽形n掺杂区（5）的掺杂比所述p型掺杂的内部区（6）的掺杂强得多。该半导体结构在技术上是简单的制造，并且兼容现代CMOS工艺。它形成一个输出的结构，特别是对于具有改进的电性能，例如电流增益和频率响应的垂直型PNP晶体管。

3. 发明申请

WO00041243A1 FIELD ISOLATED INTEGRATED INJECTION LOGIC GATE 审中-公开
标题翻译：现场隔离集成注入逻辑门
公开(公告)号：WO00041243A1
公开(公告)日：2000-07-13
申请号：PCT/EP1999/010213
申请日：1999-12-17
IPC分类号： H01L21/331 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/73
CPC分类号： H01L21/8226 , H01L27/0237
摘要： An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside down NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I2L gate and allowing more freedom in optimizing the gain of the I2L gate.
摘要翻译：提供了一种集成注入逻辑器件，其中I2L栅极的每个集电极由场氧化物（“FOX”）隔离，或通过其他合适的隔离，例如隔离沟槽隔离。使用掩埋p型层（图中示出本发明的图中的TN3），在场氧化物的下面，将基底与集电体之间，集电体的底部接触区域和集电体的底部之间的连接制成。因为硅化物和重注入物p +植入物仅存在于基极接触点处，所以复合电流降低。这与已知装置的电流损耗相比降低了电流损耗。此外，通过在集成逻辑器件中靠近NPN晶体管上颠倒的发射极放置深基极注入，也可以提高电流增益。底座的面积和收集器的面积被去耦合，即可以独立地调整基极到集电极区域和基极接触面积，以控制总基极电流，从而允许I2L栅极的布局优化更多的自由度，并允许更优化I2L门增益的自由度。

4. 发明申请

WO00019535A1 SEMICONDUCTOR STRUCTURE FOR SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体元件的半导体结构
公开(公告)号：WO00019535A1
公开(公告)日：2000-04-06
申请号：PCT/EP1999/007226
申请日：1999-09-29
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a semiconductor structure for producing semiconductor components, for example PNP transistors. The inventive semiconductor structure has a trough-shaped n-doped area (5) in a p-doped semiconductor material (1, 2), said trough encompassing a p-doped inner area (6) which extends as far as the surface of the semiconductor material. The trough-shaped n-doped area (5) is much more strongly doped that the p-doped inner area (6). The semiconductor structure is technologically simple to produce and is compatible with modern CMOS processes. The structure forms an output structure, especially for a vertical PNP transistor, with improved electrical properties, for example current amplification and frequency characteristics.
摘要翻译：用于半导体器件，例如PNP晶体管的制造中的半导体结构具有在p型掺杂的半导体材料的槽形n掺杂区（5）（1，2）（一个在到达p型掺杂的内部区6中的半导体材料的表面）包围。槽形n掺杂区（5）具有比p掺杂内区（6）的掺杂强得多的掺杂。半导体结构在技术上容易制造并且与现代CMOS工艺兼容。它形成了一个输出结构，特别是对于具有改进的电性能（例如电流增益和频率响应）的垂直PNP晶体管。

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