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1. 发明申请

WO0019535B1 SEMICONDUCTOR STRUCTURE FOR SEMICONDUCTOR COMPONENTS 审中-公开
标题翻译：半导体结构半导体器件
公开(公告)号：WO0019535B1
公开(公告)日：2000-05-11
申请号：PCT/EP9907226
申请日：1999-09-29
申请人： GRUETZEDIEK URSULA , SCHEERER JUTTA , GRUETZEDIEK HARTMUT , SCHEERER JOACHIM
发明人： GRUETZEDIEK HARTMUT , SCHEERER JOACHIM
IPC分类号： H01L21/331 , H01L21/337 , H01L21/8222 , H01L21/8226 , H01L27/02 , H01L27/082 , H01L29/732 , H01L29/808 , H01L31/10
CPC分类号： H01L29/66272 , H01L21/8222 , H01L21/8226 , H01L27/0233 , H01L27/082
摘要： The invention relates to a semiconductor structure for producing semiconductor components, for example PNP transistors. The inventive semiconductor structure has a trough-shaped n-doped area (5) in a p-doped semiconductor material (1, 2), said trough encompassing a p-doped inner area (6) which extends as far as the surface of the semiconductor material. The trough-shaped n-doped area (5) is much more strongly doped that the p-doped inner area (6). The semiconductor structure is technologically simple to produce and is compatible with modern CMOS processes. The structure forms an output structure, especially for a vertical PNP transistor, with improved electrical properties, for example current amplification and frequency characteristics.
摘要翻译：用于半导体器件，例如PNP晶体管的制造中的半导体结构具有在p型掺杂的半导体材料的槽形n掺杂区（5）（1，2）（一个在到达p型掺杂的内部区6中的半导体材料的表面）包围。槽形n掺杂区（5）的掺杂比所述p型掺杂的内部区（6）的掺杂强得多。该半导体结构在技术上是简单的制造，并且兼容现代CMOS工艺。它形成一个输出的结构，特别是对于具有改进的电性能，例如电流增益和频率响应的垂直型PNP晶体管。

2. 发明申请

WO2005098960A3 BIPOLAR-TRANSISTOR AND METHOD FOR THE PRODUCTION OF A BIPOLAR-TRANSISTOR 审中-公开
标题翻译：双极型晶体管及其制造方法双极晶体管
公开(公告)号：WO2005098960A3
公开(公告)日：2006-04-20
申请号：PCT/EP2005003129
申请日：2005-03-24
申请人： PREMA SEMICONDUCTOR GMBH , GRUETZEDIEK HARTMUT , RAMMENSEE MICHAEL , SCHEERER JOACHIM
发明人： GRUETZEDIEK HARTMUT , RAMMENSEE MICHAEL , SCHEERER JOACHIM
IPC分类号： H01L29/732 , H01L21/331 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66272 , H01L29/0615 , H01L29/0821 , H01L29/7322
摘要： The invention relates to NPN and PNP bipolar transistors and to a method for the production thereof, said transistors being characterised by a particularly high collector-emitter and collector-base blocking voltage. The blocking voltage is increased by a particular doping profile. An NPN bipolar transistor comprises a p-doped substrate (1), a trenched n-doped layer (3) forming the collector, a p-doped layer (7) which is arranged above the trenched n-doped layer and is made of a base and an n-doped layer which is arranged within the p-doped layer and forms an emitter of the transistor. A spatial charge area (RLZ 1) is formed between the p-doped layer and the trenched n-doped layer and a second spatial charge area (RLZ 2) is formed between the trenched n-doped layer and the p-doped substrate, which expands in the vertical direction on the collector when the transistor is operated with an increasing potential. The trenched n-doped layer comprises a doping profile in such a manner that when the transistor is operated with an increasing potential, the first and the second spatial charge area expand on the collector, transversing the entire depth of the trenched n-doped layer prior to the critical field strength for a breakthrough being reached between the collector and emitter.
摘要翻译：本发明涉及一种NPN和PNP双极型晶体管及其制造相同，其特征在于特别高的集电极 - 发射极和集电极 - 基极反向电压的方法。在反向电压的增加是通过特殊掺杂分布来实现的。在具有p型掺杂的衬底1，掩埋的n型层3所形成的集电极，一个掩埋n型层布置p掺杂层参照图7，基座上方并设置在p掺杂层的n掺杂层内的NPN型双极晶体管所述晶体管的发射极。形成有p型掺杂层和掩埋的n型层和第二空间电荷区RLZ 2之间的第一空间电荷区RLZ 1之间的掩埋的n型层和p型衬底从与增大的电势的晶体管的操作期间延伸在一个垂直方向上的集电体。掩埋n型层具有掺杂分布，其被创建，使得与在集电极增加潜在扩大第一和第二空间电荷区，掩埋n型层为临界场强之前整个深度的晶体管的操作期间的渗透到达集电极和发射极之间的击穿。

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