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1. 发明申请

WO9727537A3 A PROCESSOR FOR EXECUTING INSTRUCTION SETS RECEIVED FROM A NETWORK OR FROM A LOCAL MEMORY 审中-公开
标题翻译：用于执行从网络或本地存储器接收到的指令集的处理器
公开(公告)号：WO9727537A3
公开(公告)日：1997-10-16
申请号：PCT/US9701307
申请日：1997-01-23
申请人： SUN MICROSYSTEMS INC
发明人： TREMBLAY MARC , O'CONNOR JAMES MICHAEL
IPC分类号： G06F9/30 , G06F9/318 , G06F9/345 , G06F9/38 , G06F9/40 , G06F9/42 , G06F9/445 , G06F9/455 , G06F12/08 , G06F12/14 , G06F15/78
CPC分类号： G06F9/3822 , G06F9/30021 , G06F9/30134 , G06F9/30174 , G06F9/30189 , G06F9/345 , G06F9/443 , G06F9/44589 , G06F9/45504 , G06F12/0875 , G06F12/1441 , G06F15/7846 , G06F2212/451
摘要： A dual instruction set processor decodes and executes code received from a network and code supplied from a local memory. Thus, the dual instruction set processor is capable of executing instructions in two different instructions sets from two different sources. The dual instruction set processor includes a computer platform independent instruction decoder, another decoder, and an execution unit that executes decoded instructions from both of the decoders. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an Intranet, can be optimized to execute, for example, JAVA code, in example of one set of computer platform independent instructions, from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.

2. 发明申请

WO1997027544A1 PROCESSOR WITH ACCELERATED ARRAY ACCESS BOUNDS CHECKING 审中-公开
标题翻译：具有加速阵列访问边界检查的处理器
公开(公告)号：WO1997027544A1
公开(公告)日：1997-07-31
申请号：PCT/US1997001305
申请日：1997-01-23
申请人： SUN MICROSYSTEMS, INC.
发明人： SUN MICROSYSTEMS, INC. , TREMBLAY, Marc , O'CONNOR, James, Michael , JOY, William, N.
IPC分类号： G06F12/14
CPC分类号： G06F9/30021 , G06F9/264 , G06F9/30134 , G06F9/30174 , G06F9/345 , G06F9/44589 , G06F9/4484 , G06F9/449 , G06F9/45504 , G06F12/0875 , G06F12/1441 , G06F2212/451
摘要： An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element. A first comparison element compares the value of the referenced element and the maximum array index boundary value and provides a maximum violation signal if the value of the element is greater than the maximum array size boundary value. A second comparison element compares the value of the element and the minimum array size boundary value and provides a minimum violation signal if the value of the element is less than the minimum array bounds value. Either a maximum violation signal or a minimum violation signal results in an exception.
摘要翻译：阵列边界检查装置被配置为验证信息阵列的引用元素在最大数组大小边界值和最小数组大小边界值内。本发明的阵列边界检查装置包括存储和检索多个阵列绑定值的关联存储元件。多个阵列绑定值中的每一个与多个阵列访问指令之一相关联。输入部分同时将数组访问指令标识符与每个存储的数组参考条目的至少一部分进行比较，其中数组访问指令标识符标识数组访问指令。输出部分被配置为提供作为阵列的输出值，存储在相关联的存储器元件的多个存储器位置之一中的多个阵列约束值之一。第一个比较元素比较引用元素的值和最大数组索引边界值，如果元素的值大于最大数组大小边界值，则提供最大违规信号。第二比较元素比较元素的值和最小数组大小边界值，并且如果元素的值小于最小数组边界值，则提供最小违规信号。最大违规信号或最小违规信号都会导致异常。

3. 发明申请

WO2016009168A1 CALL STACK MAINTENANCE FOR A TRANSACTIONAL DATA PROCESSING EXECUTION MODE 审中-公开
标题翻译：调用数据处理执行模式的堆栈维护
公开(公告)号：WO2016009168A1
公开(公告)日：2016-01-21
申请号：PCT/GB2015/051675
申请日：2015-06-09
申请人： ARM LIMITED
发明人： HORSNELL, Matthew James , DIESTELHORST, Stephan
IPC分类号： G06F9/46 , G06F9/30 , G06F9/38
CPC分类号： G06F9/467 , G06F9/528 , G06F12/0811 , G06F12/0875 , G06F12/0891 , G06F12/128 , G06F2212/1032 , G06F2212/451 , G06F2212/621
摘要： A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative. Conversely if the modification to the call stack is to be made at a relative stacking position which is not in a positive growth direction with respect to the position indicated by the copy stored, then that modification is labelled as speculative. The size of the write-set associated with maintaining the call stack whilst in transactional execution mode can therefore be reduced.
摘要翻译：提供了一种数据处理装置和数据处理方法，其涉及根据执行的数据处理指令来维护调用堆栈的处理器的操作。处理器被配置为当数据处理指令寻求访问与另外的处理器共享的存储数据项时，以事务执行模式操作。当处理器进入其事务执行模式时，它存储当前堆栈深度指示的副本，此后，当在其事务执行模式下操作时，对调用堆栈的进一步修改与存储的堆栈深度指示的副本进行比较。如果所需修改的相对堆叠位置相对于存储的副本处于正的堆叠增长方向，则对该调用栈的修改被标记为非推测性的。相反，如果对相对于所存储的副本所指示的位置处于正增长方向的相对堆叠位置进行对调用堆栈的修改，则该修改被标记为推测。因此可以减少在事务执行模式期间与保持调用堆栈相关联的写入组的大小。

4. 发明申请

WO2015081889A1 一种缓存系统和方法审中-公开
公开(公告)号：WO2015081889A1
公开(公告)日：2015-06-11
申请号：PCT/CN2014/093150
申请日：2014-12-05
申请人：上海芯豪微电子有限公司
发明人：林正浩
IPC分类号： G06F9/30 , G06F12/02
CPC分类号： G06F12/0868 , G06F9/383 , G06F12/0862 , G06F12/0895 , G06F2212/1021 , G06F2212/281 , G06F2212/282 , G06F2212/451
摘要：本发明提供了一种缓存系统和方法，应用于处理器领域时能区分数据缓存中位于栈区域和非栈区域的数据，并提供独立的栈缓存用于存放栈区域中的数据；在处理器核执行数据访问指令前，提前在栈缓存中分配数据存储单元，使得该数据访问指令对应的数据在栈缓存中一定命中。

5. 发明申请

WO2016126523A3 AUTHENTICATED CONTROL STACKS 审中-公开
标题翻译：认证控制堆
公开(公告)号：WO2016126523A3
公开(公告)日：2016-09-29
申请号：PCT/US2016015438
申请日：2016-01-28
申请人： QUALCOMM INC
发明人： KRISHNASWAMY ARVIND , ACAR CAN , TURNER ROBERT
IPC分类号： G06F21/52 , G06F11/10 , G06F12/08 , G06F15/78
CPC分类号： G06F21/52 , G06F11/10 , G06F12/0875 , G06F15/7846 , G06F21/44 , G06F21/51 , G06F2212/451
摘要： A method of producing a control stack includes: writing a plurality of control information entries into a control stack buffer that is internal to a processor in response to one or more function calls; and in response to the control stack buffer being full and receiving a further function call, writing: the plurality of control information entries to an external memory that is external to the processor; and a further control information entry, corresponding to the further function call, to the control stack buffer.
摘要翻译：一种产生控制堆栈的方法包括：响应于一个或多个功能调用将多个控制信息条目写入处理器内部的控制堆栈缓冲器; 并且响应于所述控制堆栈缓冲器已满并接收另外的功能调用，将所述多个控制信息条目写入到处理器外部的外部存储器; 以及对应于进一步的功能调用的另一个控制信息条目提供给控制栈缓冲器。

6. 发明申请

WO0122213A3 OPTIMIZED BYTECODE INTERPRETER OF VIRTUAL MACHINE INSTRUCTIONS 审中-公开
标题翻译：虚拟机指令的优化BYODECODE解释器
公开(公告)号：WO0122213A3
公开(公告)日：2001-11-29
申请号：PCT/EP0008976
申请日：2000-09-13
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： RICCARDI FABIO
IPC分类号： G06F9/318 , G06F9/00 , G06F9/45
CPC分类号： G06F9/45516 , G06F2212/451
摘要： The invention relates to a method of optimizing interpreted programs, in a virtual machine interpreter of a bytecode-based language, comprising means for dynamically reconfiguring said virtual machine with macro operation codes by replacing an original sequence of simple operation codes with a new sequence of said macro operation codes. The virtual machine interpreter is coded as an indirect threading interpreter thanks to a translation table containing the implementation addresses of the operation codes for translating the bytecodes into the operation code's implementation addresses. Application: embedded systems using any bytecode-based programming language, set to box for interactive video transmissions.
摘要翻译：本发明涉及一种在基于字节码的语言的虚拟机解释器中优化解释程序的方法，该方法包括用于利用宏操作码来动态地重新配置所述虚拟机的装置，其中通过用新的所述序列宏操作码。由于翻译表包含用于将字节码转换为操作码的实施地址的操作码的实施地址，所以虚拟机解释器被编码为间接线程解释器。应用程序：使用任何基于字节码的编程语言的嵌入式系统，设置为用于交互式视频传输的框。

7. 发明申请

WO01022213A2 OPTIMIZED BYTECODE INTERPRETER OF VIRTUAL MACHINE INSTRUCTIONS 审中-公开
标题翻译：虚拟机指令优化解码器
公开(公告)号：WO01022213A2
公开(公告)日：2001-03-29
申请号：PCT/EP2000/008976
申请日：2000-09-13
IPC分类号： G06F9/318 , G06F9/00 , G06F9/45
CPC分类号： G06F9/45516 , G06F2212/451
摘要： The invention relates to a method of optimizing interpreted programs, in a virtual machine interpreter of a bytecode-based language, comprising means for dynamically reconfiguring said virtual machine with macro operation codes by replacing an original sequence of simple operation codes with a new sequence of said macro operation codes. The virtual machine interpreter is coded as an indirect threading interpreter thanks to a translation table containing the implementation addresses of the operation codes for translating the bytecodes into the operation code's implementation addresses. Application: embedded systems using any bytecode-based programming language, set to box for interactive video transmissions.
摘要翻译：本发明涉及一种在基于字节代码的语言的虚拟机解释器中优化解释程序的方法，包括：用宏操作代码动态重新配置所述虚拟机的装置，通过用所述的新序列代替简单操作代码的原始序列宏操作代码。由于包含用于将字节码转换为操作代码的实现地址的操作代码的实现地址的转换表，虚拟机解释器被编码为间接线程解释器。应用：使用任何基于字节码的编程语言的嵌入式系统，设置为交互式视频传输的框。

8. 发明申请

WO1997027537A2 A PROCESSOR FOR EXECUTING INSTRUCTION SETS RECEIVED FROM A NETWORK OR FROM A LOCAL MEMORY 审中-公开
标题翻译：用于执行从网络或本地存储器接收到的指令集的处理器
公开(公告)号：WO1997027537A2
公开(公告)日：1997-07-31
申请号：PCT/US1997001307
申请日：1997-01-23
申请人： SUN MICROSYSTEMS, INC.
发明人： SUN MICROSYSTEMS, INC. , TREMBLAY, Marc , O'CONNOR, James, Michael
IPC分类号： G06F09/318
CPC分类号： G06F9/3822 , G06F9/30021 , G06F9/30134 , G06F9/30174 , G06F9/30189 , G06F9/345 , G06F9/44589 , G06F9/449 , G06F9/45504 , G06F12/0875 , G06F12/1441 , G06F15/7846 , G06F2212/451
摘要： A dual instruction set processor can decode and execute both code received from a network and other code supplied from a local memory. Thus, the dual instruction set processor is capable of executing two different types of instructions, from two different sources, permitting the dual instruction set processor to have maximum efficiency. A computer system with the foregoing described dual instruction set processor, a local memory, and a communication interface device, such as a modem, for connection to a network, such as the Internet or an intranet, can be optimized to execute, for example, JAVA code from the network, and to execute non-JAVA code stored locally, or on the network but in a trusted environment or an authorized environment.
摘要翻译：双指令集处理器可以解码和执行从网络接收的代码和从本地存储器提供的其他代码。因此，双指令集处理器能够从两个不同的源执行两种不同类型的指令，允许双指令集处理器具有最大的效率。可以优化具有上述双指令集处理器，本地存储器和用于连接到诸如因特网或内联网的网络的调制解调器的通信接口设备的计算机系统，以执行例如，来自网络的JAVA代码，并且执行在本地存储的本地或在网络上但在受信任的环境或授权环境中的非JAVA代码。

9. 发明申请

WO1997027536A1 INSTRUCTION FOLDING FOR A STACK-BASED MACHINE 审中-公开
标题翻译：基于堆叠机的指导折叠
公开(公告)号：WO1997027536A1
公开(公告)日：1997-07-31
申请号：PCT/US1997001221
申请日：1997-01-23
申请人： SUN MICROSYSTEMS, INC.
发明人： SUN MICROSYSTEMS, INC. , O'CONNOR, James, Michael , TREMBLAY, Marc
IPC分类号： G06F09/318
CPC分类号： G06F9/30021 , G06F9/30134 , G06F9/30174 , G06F9/30181 , G06F9/345 , G06F9/3879 , G06F9/44589 , G06F9/4484 , G06F9/449 , G06F9/45504 , G06F12/0875 , G06F2212/451 , Y02D10/13
摘要： An instruction decoder (135, 1118) allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack (e.g., 423, 155, 812) merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction sequences and supplies an execution unit with a single equivalent folded operation thereby reducing processing cycles otherwise required for execution of multiple operations corresponding to the multiple instructions of the folded instruction sequence. Instruction decoder embodiments described herein provide for folding of two, three, four, or more instruction folding. For example, in one instruction decoder embodiment described herein, two load instructions and a store instruction can be folded into execution of operation corresponding to an instruction appearing therebetween in the instruction sequence.
摘要翻译：指令解码器（135,1118）允许将JAVA虚拟机指令折叠起来将操作数推送到堆栈顶部（例如，423,155,812），仅作为在第二JAVA虚拟机指令上操作的第二JAVA虚拟机指令的前身堆栈操作数顶部。这种指令解码器识别可折叠指令序列并且向执行单元提供单个等效折叠操作，从而减少执行与折叠指令序列的多个指令相对应的多个操作所需的处理循环。这里描述的指令解码器实施例提供折叠两个，三个，四个或更多个指令折叠。例如，在这里描述的一个指令解码器实施例中，可以将两个加载指令和存储指令折叠成与在指令序列中出现的指令相对应的操作的执行。

10. 发明申请

WO1995030954A1 DATA CACHE 审中-公开
标题翻译：数据缓存
公开(公告)号：WO1995030954A1
公开(公告)日：1995-11-16
申请号：PCT/GB1995000827
申请日：1995-04-11
申请人： THE SECRETARY OF STATE FOR DEFENCE , FIELD-RICHARDS, Hugh, Sherwood , WISEMAN, Simon, Robert
发明人： THE SECRETARY OF STATE FOR DEFENCE
IPC分类号： G06F09/38
CPC分类号： G06F9/3875 , G06F9/30134 , G06F9/3824 , G06F9/3869 , G06F12/0853 , G06F12/0855 , G06F12/0875 , G06F2212/451
摘要： A Data Cache (22) for a stack based computer (10) comprises an address calculation stage (25), a cache maintenance stage (26) and an arithmetic logic unit stage (27). The computer (10) comprises external memory (21) and a pipelined processor (20). An instruction from an instruction fetch stage (24) is passed to the address calculation stage (25). The address calculation stage (25) translates addresses relative to the top of stack into an absolute address. The cache maintenance stage receives the absolute addresses and determines if data corresponding to the addresses is available in a temporary register in the ALU stage (25). If necessary, the cache maintenance stage (26) injects read from or write to memory instructions into the pipeline (28).
摘要翻译：用于基于堆栈的计算机（10）的数据高速缓存（22）包括地址计算级（25），高速缓存维护级（26）和算术逻辑单元级（27）。计算机（10）包括外部存储器（21）和流水线处理器（20）。指令提取级（24）的指令被传递到地址计算级（25）。地址计算阶段（25）将相对于堆栈顶部的地址转换为绝对地址。高速缓存维护阶段接收绝对地址，并确定与ALU阶段（25）中的临时寄存器中的地址对应的数据是否可用。如果需要，缓存维护阶段（26）将从存储器指令读取或写入管线（28）中注入。

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