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1. 发明申请

WO00074238A1 DIGITAL VOLTAGE CONTROLLED OSCILLATOR 审中-公开
标题翻译：数字电压控制振荡器
公开(公告)号：WO00074238A1
公开(公告)日：2000-12-07
申请号：PCT/US2000/014646
申请日：2000-05-26
IPC分类号： G06F1/03 , H02M7/48 , H02M7/493 , H03K3/02
CPC分类号： H02M7/493 , G06F1/0321 , G06F1/0342
摘要： A digital voltage controlled oscillator is disclosed. The digital voltage controlled oscillator includes an input for receiving input signals representative of a desired frequency. It also includes a pulse generator and a logic circuit. The logic circuit develops an oscillating signal having a predefined waveform and the desired frequency by controlling the energy contained in the pulses output by the pulse generator. The disclosed digital voltage controlled oscillator also includes a capacitor which is charged by the pulses to a voltage that generally varies in accordance with the predefined waveform and the desired frequency.
摘要翻译：公开了一种数字压控振荡器。数字压控振荡器包括用于接收表示期望频率的输入信号的输入端。它还包括一个脉冲发生器和一个逻辑电路。逻辑电路通过控制包含在由脉冲发生器输出的脉冲中的能量来形成具有预定波形和期望频率的振荡信号。所公开的数字压控振荡器还包括电容器，其被脉冲充电到通常根据预定波形和期望频率而变化的电压。

2. 发明申请

WO2009114252A1 DIGITAL FREQUENCY SYNTHESIS 审中-公开
标题翻译：数字频率合成
公开(公告)号：WO2009114252A1
公开(公告)日：2009-09-17
申请号：PCT/US2009/034776
申请日：2009-02-20
申请人： XILINX, INC.
发明人： DICK, Christopher, H. , HARRIS, Fredric, J.
IPC分类号： G06F1/03
CPC分类号： G06F1/0328 , G06F1/0342
摘要： Method and apparatus for digital frequency synthesis are described. A frequency synthesizer (200) has an accumulator (201 ), an adder (204), and a predictive filter (208). The adder (204) is configured to subtract a predicted error from a phase profile signal. A quantized version of the phase profile signal is separated from an error portion thereof. The predictive filter (208), set for a fraction of a sample frequency bandwidth, is coupled to receive the error portion for generation of a next predicted error. A storage device (206) has digital representations of sinusoidal signals accessible responsive to the quantized version of the phase profile signal. A digital-to-analog converter (209) is coupled to receive a digital representation of a sinusoidal signal obtained from the storage device (206) to provide an analog sinusoidal signal. An anti-imaging filter (210) is coupled to receive the analog sinusoidal signal and configured to filter out noise.
摘要翻译：描述了用于数字频率合成的方法和装置。频率合成器（200）具有累加器（201），加法器（204）和预测滤波器（208）。加法器（204）被配置为从相位轮廓信号中减去预测误差。相位曲线信号的量化版本与其误差部分分离。设置为采样频率带宽的一小部分的预测滤波器（208）被耦合以接收用于产生下一预测误差的误差部分。存储装置（206）具有响应于相位轮廓信号的量化版本可访问的正弦信号的数字表示。数模转换器（209）被耦合以接收从存储装置（206）获得的正弦信号的数字表示，以提供模拟正弦信号。耦合抗成像滤光器（210）以接收模拟正弦信号并且被配置为滤除噪声。

3. 发明申请

WO00074223A1 METHODS AND APPARATUS FOR LOAD SHARING BETWEEN PARALLEL INVERTERS IN AN AC POWER SUPPLY 审中-公开
标题翻译：交流电源并联逆变器之间负载共享的方法与装置
公开(公告)号：WO00074223A1
公开(公告)日：2000-12-07
申请号：PCT/US2000/014647
申请日：2000-05-26
IPC分类号： G06F1/03 , H02M7/48 , H02M7/493
CPC分类号： H02M7/493 , G06F1/0321 , G06F1/0342
摘要： Methods and apparatus are disclosed for achieving load balance between parallel inverters in an AC power supply. Load balancing reduces undesirable cross conduction current between the parallel inverters. Load balancing and the resulting reduction in cross conduction current are achieved without the need for common control circuitry between the parallel inverters. Thus, the single-fault protection offered by redundant parallel inverters is not compromised by the disclosed load balancing techniques.
摘要翻译：公开了用于实现交流电源中的并联逆变器之间的负载平衡的方法和装置。负载平衡可降低并联逆变器之间的不必要的交叉传导电流。在不需要并联逆变器之间的公共控制电路的情况下，实现负载平衡和所导致的交叉传导电流的降低。因此，冗余并联逆变器提供的单故障保护不受所公开的负载均衡技术的影响。

4. 发明申请

WO2016122767A1 APPARATUS AND METHOD FOR EFFICIENT WAVEFORM PORTABILITY BETWEEN DIFFERENT PLATFORMS 审中-公开
标题翻译：不同平台之间有效波动易用性的装置和方法
公开(公告)号：WO2016122767A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/062797
申请日：2015-11-25
申请人： RAYTHEON COMPANY
发明人： MARR, Harry B. , ROBINSON, Ian S. , HSU, Ray, Ten-Shing
IPC分类号： H04K3/00
CPC分类号： H04B7/0613 , G06F1/0342 , H03K19/17708 , H04K3/42 , H04K3/44
摘要： Method and apparatus for generating channelized hardware-independent waveforms include: generating metadata associated with a waveform, the metadata including a frequency list, a phase list and amplitude information, wherein the metadata is generated independent of a number of channels; interpreting the metadata to generate channel select, frequency, phase and amplitude parameters; providing the frequency, phase and amplitude parameters to a direct digital synthesizer (DDS) to generate a digital signal; providing the channel select parameter to a channel selector to generate a plurality of channelized waveforms from the generated digital signal; and transmitting the plurality of channelized waveforms over a plurality of communication channels.
摘要翻译：用于产生信道化与硬件无关的波形的方法和装置包括：生成与波形相关联的元数据，所述元数据包括频率列表，相位列表和幅度信息，其中独立于多个信道生成所述元数据; 解释元数据以产生通道选择，频率，相位和幅度参数; 将频率，相位和幅度参数提供给直接数字合成器（DDS）以产生数字信号; 向频道选择器提供频道选择参数以从所生成的数字信号中产生多个信道化波形; 以及在多个通信信道上发送多个信道化波形。

5. 发明申请

WO2014053301A1 METHOD AND APPARATUS FOR QUADRATURE MIXER CIRCUITS 审中-公开
标题翻译：方法和装置用于平衡混合器电路
公开(公告)号：WO2014053301A1
公开(公告)日：2014-04-10
申请号：PCT/EP2013/069162
申请日：2013-09-16
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： SUNDSTRÖM, Lars , EK, Staffan
IPC分类号： H03D7/16 , G06F1/03 , H04L27/38
CPC分类号： G06F1/0342 , H03D7/165
摘要： The teachings presented herein allow the same sequence of local oscillator waveform sample values to be used for driving two harmonic rejection mixers for which quadrature operation is desired, irrespective of whether the oversampling rate of the sequence is divisible by four or only divisible by two. This ability is obtained by controlling whether the quadrature mixer clocks coincidentally with the ίη-phase mixer, or clocks a half clock cycle out of phase relative to the in-phase mixer. Several advantages attend the contemplated circuit arrangement and method of operation. Example advantages include the improved matching that comes from operating both mixers with the identical waveform sample values, and the improved flexibility in optimizing the harmonic rejection and/or interference- related operation of the mixers over a broader range of frequencies of interest, which flows from having a larger set of usable OSRs.
摘要翻译：本文给出的教导允许使用相同的本地振荡器波形采样值序列来驱动需要进行正交操作的两个谐波抑制混频器，而不管序列的过采样率是否可被四除或仅可被二除。该能力通过控制正交混频器的时钟与相位混频器是否相符，或者相位相位混频器的时钟周期不同步来获得。几个优点参加了预期的电路装置和操作方法。示例优点包括来自使用具有相同波形采样值的两个混频器的改进匹配，以及在更广泛的感兴趣的频率范围内优化混频器的谐波抑制和/或干扰相关操作的改进的灵活性，其从具有更大的一组可用的OSR。

6. 发明申请

WO1997018623A1 SYSTEM, METHOD AND PROGRAM PRODUCT FOR GENERATING A SINE OR COSINE WAVEFORM UTILIZING COMBINED LOOK-UP TABLES 审中-公开
标题翻译：用于生成使用组合查看表的正弦波或卫星波形的系统，方法和程序产品
公开(公告)号：WO1997018623A1
公开(公告)日：1997-05-22
申请号：PCT/KR1996000162
申请日：1996-09-17
申请人： SAMSUNG ELECTRONICS CO., LTD. , KWAK, Mal, Seob
发明人： SAMSUNG ELECTRONICS CO., LTD.
IPC分类号： H03B28/00
CPC分类号： G06F1/0342
摘要： A method, system or program product for generating a sine waveform and a cosine waveform is provided by providing in a first look-up table (24) data corresponding to quantized values of a portion of the period of a cosine waveform and providing in a second look-up table (25) data corresponding to quantized values of a portion of the period of a sine waveform corresponding to the period of the cosine waveform quantized values from both the first (24) and the second (25) look-up tables may be to generate a sine waveform. Furthermore, quantized values from both the first (24) and the second (25) look-up tables may also be utilized to generate a cosine waveform.
摘要翻译：通过在第一查询表（24）中提供对应于余弦波形的周期的一部分的量化值的数据来提供用于产生正弦波形和余弦波形的方法，系统或程序产品，并提供第二对应于与来自第一（24）和第二（25）查找表两者的余弦波形的量化值的周期相对应的正弦波形的周期的一部分的量化值的查找表（25）数据可以要产生正弦波形。此外，也可以利用来自第一（24）和第二（25）查找表的量化值来产生余弦波形。

7. 发明申请

WO2013109694A1 HIGH ACCURACY SIN-COS WAVE AND FREQUENCY GENERATORS, AND RELATED SYSTEMS AND METHODS 审中-公开
标题翻译：高精度SIN-COS波和频率发生器及相关系统和方法
公开(公告)号：WO2013109694A1
公开(公告)日：2013-07-25
申请号：PCT/US2013/021844
申请日：2013-01-17
申请人： QUALCOMM INCORPORATED
发明人： HOYLE, David J.
IPC分类号： G06F1/035 , G06F1/03
CPC分类号： G06F1/0356 , G06F1/0342 , G06F1/0353 , G06F2101/04
摘要： High accuracy sin-cos wave and frequency generators, and related systems and methods. In non-limiting embodiments disclosed herein, the sin-cos wave generators can provide highly accurate sin-cos values for sin-cos wave generation with low hardware costs and small lookup table requirements. The embodiments disclosed herein may include a circuit to conduct an arithmetic approximation of a sin-cos curve based on a phase input. The circuit may be in communication with a point lookup table and a correction lookup table. The tables may receive the phase input and match the phase input to main sin-cos endpoints associated with the phase, and to a correction value for the phase. These values which are selected based on the phase input, may be communicated to a converter circuit where the arithmetic functions are applied to the values resulting in a sin-cos curve value.
摘要翻译：高精度正弦波和频率发生器及相关系统和方法。在本文公开的非限制性实施例中，正弦波发生器可以以低硬件成本和小的查找表要求为正弦波产生提供高精度的sin-cos值。本文公开的实施例可以包括基于相位输入进行sin-cos曲线的算术近似的电路。电路可以与点查找表和校正查找表通信。这些表可以接收相位输入并将相位输入匹配到与相位相关联的主sin-cos端点，以及相位的校正值。基于相位输入选择的这些值可以传送到转换器电路，其中将算术函数应用于产生sin-cos曲线值的值。

8. 发明申请

WO2011126619A1 METHODS AND APPARATUS FOR TRANSMISSION OF DATA 审中-公开
标题翻译：用于传输数据的方法和装置
公开(公告)号：WO2011126619A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/026380
申请日：2011-02-26
申请人： RAMBUS INC. , BUCHER, Michael , WILSON, John
发明人： BUCHER, Michael , WILSON, John
IPC分类号： G11C7/22 , G11C8/00
CPC分类号： G11C7/1051 , G06F1/0342 , G06F1/04 , G06F1/06 , G06F13/38 , G06F13/4243 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , H04B3/32 , H04L7/0008 , H04L25/026 , H04L25/0264
摘要： A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation.
摘要翻译：一种系统包括通过传输线耦合在一起的发射机电路和接收机电路。发射机电路产生早期定时信号，标称定时信号和延迟定时信号。多路复用器电路基于数据信号在早期和晚期定时信号之间进行选择，以产生对数据信号进行编码的编码输出信号。标称定时信号和编码的输出信号通过传输线传输到接收器电路。接收器电路响应于标称定时信号对编码的输出信号进行采样，以产生偶数和奇数采样数据信号。互补定时信号可以通过编码输出信号相对侧的传输线传输，以提供串扰消除。

9. 发明申请

WO2006012493A1 HIGH-ORDER DELTA-SIGMA NOISE SHAPING IN DIRECT DIGITAL FREQUENCY SYNTHESIS 审中-公开
标题翻译：直接数字频率合成中的高阶DELTA-SIGMA噪声形状
公开(公告)号：WO2006012493A1
公开(公告)日：2006-02-02
申请号：PCT/US2005/026007
申请日：2005-07-22
申请人： AUBURN UNIVERSITY , DAI, Fa
发明人： DAI, Fa
IPC分类号： G06F1/03
CPC分类号： H03M7/3042 , G06F1/0328 , G06F1/0342 , H03L7/16 , H03M7/3026
摘要： A direct digital synthesis (DDS) circuit utilizes high order delta-sigma interpolators to remove frequency, phase and amplitude domain quantization errors. The DDS employs an n-bit accumulator operative for receiving an input frequency word (FCW) representing the desired frequency output and converts the frequency word to phase information based upon the clock frequency of the DDS. A highorder delta-sigma interpolator is configured in frequency, phase or amplitude domain to noise-shape the quantization errors through a unit defined by the transfer function of 1-(1-z 1)1( in either a feedforward or feedback manner. The delta-sigma interpolator of any order can be implemented using a single-stage pipelined topology with noise transfer function of (1-zIf . The DDS circuit also includes digital-to-analog converters (DACs) that convert the outputted sine and cosine amplitude words to analog sinusoidal quardrature signals; and deglitch analog lowpass filters that remove the small glitches due to data conversion.
摘要翻译：直接数字合成（DDS）电路利用高阶Δ-sigma内插器去除频率，相位和幅度域量化误差。 DDS使用n位累加器，用于接收表示所需频率输出的输入频率字（FCW），并根据DDS的时钟频率将频率字转换为相位信息。高频delta-sigma内插器被配置在频率，相位或幅度域中，以通过由1-（1-z 1）1的传递函数定义的单位（以前馈或反馈方式）对量化误差进行噪声整形。可以使用具有（1-zIf）噪声传递函数的单级流水线拓扑来实现任何顺序的Δ-sigma内插器，DDS电路还包括转换输出的正弦和余弦幅度字的数模转换器（DAC）模拟正弦曲线信号;以及去掉由于数据转换引起的小毛刺的模拟低通滤波器。

10. 发明申请

WO2017058697A1 PROTECTION TECHNIQUES FOR GENERATOR FOR DIGITALLY GENERATING ELECTROSURGICAL AND ULTRASONIC ELECTRICAL SIGNAL WAVEFORMS 审中-公开
标题翻译：用于数字生成电磁和超声波电信号波形发生器的保护技术
公开(公告)号：WO2017058697A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/053667
申请日：2016-09-26
申请人： ETHICON ENDO-SURGERY, LLC
发明人： YATES, David C. , WIENER, Eitan T.
IPC分类号： A61B18/12 , A61B17/32 , A61B18/00 , G06F1/03
CPC分类号： A61B18/1206 , A61B17/320068 , A61B17/320092 , A61B18/1445 , A61B2018/00607 , A61B2018/00678 , A61B2018/00684 , A61B2018/00994 , G06F1/0321 , G06F1/0342 , H03M1/66
摘要： A method of generating electrical signal waveforms. A generator includes a digital processing circuit, a memory circuit in communication with the digital processing circuit defining a lookup table, a digital synthesis circuit in communication with the digital processing circuit and the memory circuit, and a digital-to-analog converter (DAC) circuit. The method includes generating a first and second digital electrical signal waveforms, combining the first and second waveforms to form a combined waveform, modifying the combined waveform to form a modified waveform The peak amplitude of the modified waveform does not exceed a predetermined amplitude value. The method includes generating a second waveform that is a function of the first waveform. The method includes modifying a frequency of the first waveform to form a frequency modified first waveform and combining the frequency modified first and second waveforms to form a combined waveform.
摘要翻译：一种产生电信号波形的方法。发电机包括数字处理电路，与定义查找表的数字处理电路通信的存储电路，与数字处理电路和存储电路通信的数字合成电路，以及数模转换器（DAC）电路。该方法包括产生第一和第二数字电信号波形，组合第一和第二波形以形成组合波形，修改组合波形以形成修改波形修改波形的峰值幅度不超过预定振幅值。该方法包括产生作为第一波形的函数的第二波形。该方法包括修改第一波形的频率以形成频率修改的第一波形，并组合频率修正的第一和第二波形以形成组合波形。

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