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1. 发明申请

WO2008118346A3 VARIABLE SIZED APERTURE WINDOW OF AN ANALOG-TO-DIGITAL CONVERTER 审中-公开
标题翻译：模拟数字转换器的可变大小的窗口窗口
公开(公告)号：WO2008118346A3
公开(公告)日：2008-11-13
申请号：PCT/US2008003698
申请日：2008-03-20
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , SNIVELY LESLIE O , HUIE JOHN
发明人： MOORE CHARLES H , SNIVELY LESLIE O , HUIE JOHN
IPC分类号： H03M1/12
CPC分类号： H03M1/1245 , H03M1/1215 , H03M1/60
摘要： Sampling high frequency input analog signals and conversion to digital output signals accomplished using many analog-to- digital converters and distpbuted sampling system - combination allowing conventional device processing e g 0.18 micron silicon, and providing accurate sampling of very high frequency signals. Distributed sampling system provides multiple samplings of input using multiple ADCs collecting samplings, each offset by a fixed amount of time from the most recent. Each ADC has a designated CPU to obtain sufficient data transfer capabilities. Samplings from ADCs are a sepes of digital output values, possibly the result of samplings at the same or different frequencies. Distributed sampling systems include elongated trace patterns series-connected, inverter pairs series-connected, specific permittivity material device, and sequencer/multiplier. Another sampling system includes vanable-sized aperture window, width of sample pulse narrowed through vapable clock mechanism producing faster sampling rates. Vanable-sized aperture window system can be used solely, or in combination with others.
摘要翻译：采用高频输入模拟信号和转换为数字输出信号，使用许多模数转换器和分频采样系统进行组合，允许常规器件处理（例如0.18微米硅），并提供非常高频率信号的精确采样。分布式采样系统使用多个采集采样的ADC提供多个输入采样，每个采样偏移距离最近一段固定的时间。每个ADC都有一个指定的CPU来获得足够的数据传输能力。 ADC的采样是数字输出值的分辨率，可能是相同或不同频率的采样结果。分布式采样系统包括串联连接的细长迹线图案，串联连接的逆变器对，特定介电常数材料器件和定序器/倍增器。另一个采样系统包括可选尺寸的孔径窗口，采样脉冲宽度通过可变时钟机制变窄，产生较快的采样率。可拆式孔径窗系统可单独使用，也可与其他组合使用。

2. 发明申请

WO2010065608A3 METHOD AND APPARATUS FOR CIRCUIT SIMULATION 审中-公开
标题翻译：用于电路仿真的方法和设备
公开(公告)号：WO2010065608A3
公开(公告)日：2010-09-16
申请号：PCT/US2009066365
申请日：2009-12-02
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H
发明人： MOORE CHARLES H
IPC分类号： H01L21/66 , H01L21/02
CPC分类号： G06F17/5036
摘要： An integrated circuit simulator and method of integrated circuit simulation comprising providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type and providing a temperature lookup table having predetermined temperature data. Then simulating operation for each transistor in the integrated circuit by determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and simulating operation for each transistor in the integrated circuit by determining a transistor temperature value and incrementing a simulation time step and repeating the last two steps until simulations complete.
摘要翻译：一种集成电路仿真器和集成电路仿真方法，包括提供具有用于给定晶体管类型的预定漏极电压数据的电压查找表，提供具有用于给定晶体管类型的预定栅极电压数据的电压查找表，并提供具有预定的温度查找表温度数据。然后通过根据预定电压数据值之一和预定温度数据值中的一个确定通过晶体管的电流值来模拟集成电路中每个晶体管的操作; 以及通过确定晶体管温度值并且增加模拟时间步骤并且重复最后两个步骤直到模拟完成来模拟集成电路中的每个晶体管的操作。

3. 发明申请

WO2010056366A2 LOCALIZED CONTROL METHOD AND APPARATUS 审中-公开
标题翻译：本地化控制方法和装置
公开(公告)号：WO2010056366A2
公开(公告)日：2010-05-20
申请号：PCT/US2009006145
申请日：2009-11-17
申请人： VNS PORTFOLIO LLC , ANTONOPOULOS NICHOLAS A , SAUNDERS F ERIC , MOORE CHARLES H
发明人： ANTONOPOULOS NICHOLAS A , SAUNDERS F ERIC , MOORE CHARLES H
IPC分类号： H05B37/02
CPC分类号： H05B37/0227
摘要： A zoned interactive control area (10) wherein an architectural space is divided into a plurality of zones (16), each having its own sensor(s) and zone lights (18). The zone lights (18) are controlled by a controller (20) such that there are different lighting levels (55, 57, 59) depending upon whether a zone (16) is occupied, whether an adjacent zone (16) is occupied, whether some other zone (16) is occupied, and the like. A variable control method (50) is adaptable such that fine control and adaptation for special circumstances can be achieved. Other types of devices can also be controlled according to the present inventive method and apparatus.
摘要翻译：一种划分的交互式控制区域（10），其中建筑空间被分成多个区域（16），每个区域具有其自己的传感器和区域光（18）。区域灯（18）由控制器（20）控制，使得根据区域（16）是否被占用，相邻区域（16）是否被占用，是否存在不同的照明级别（55,57,59），是否一些其他区域（16）被占用等等。变量控制方法（50）适应性强，可以实现特殊情况的精细控制和适应。也可以根据本发明的方法和装置来控制其他类型的装置。

4. 发明申请

WO2009128925A2 MICROPROCESSOR EXTENDED INSTRUCTION SET PRECISION MODE 审中-公开
标题翻译：微处理器扩展指令精度模式
公开(公告)号：WO2009128925A2
公开(公告)日：2009-10-22
申请号：PCT/US2009002362
申请日：2009-04-15
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , BAILEY GREGORY V
发明人： MOORE CHARLES H , BAILEY GREGORY V
IPC分类号： G06F9/46 , G06F5/00 , G06F12/02 , G06F13/38
CPC分类号： G06F9/30189 , G06F9/30 , G06F9/30014 , G06F9/30181
摘要： A method and apparatus to gain additional functionality of a microprocessor by adding an extended instruction set mode. In this mode, the result of executing an instruction may be changed without changing the instruction itself. In the extended instruction set mode, there is an increase to the number of bits of precision when executing the plus instruction. An additional bit position is added to the program counter register. When this bit is set, the microprocessor is in extended instruction set mode. In addition, a new one bit latch is provided. The latch may be changed only when the microprocessor is in extended instruction set mode. The latch is defined as holding a true carry bit. A significant bit of a register holding a sum is saved in the carry latch at the end of the plus instruction.
摘要翻译：一种通过添加扩展指令集模式来获得微处理器附加功能的方法和装置。在该模式中，执行指令的结果可以改变而不改变指令本身。在扩展指令集模式下，执行加指令时，精度位数增加。一个额外的位位置被添加到程序计数器寄存器。当该位置1时，微处理器处于扩展指令集模式。另外，提供了新的一位锁存器。只有当微处理器处于扩展指令集模式时，才能更改锁存器。锁存器被定义为保持一个真正的进位位。持有总和的寄存器的有效位被保存在加号指令末尾的进位锁存器中。

5. 发明申请

WO2009154692A3 METHOD AND APPARATUS FOR LOADING DATA AND INSTRUCTIONS INTO A COMPUTER 审中-公开
标题翻译：用于将数据和指令装入计算机的方法和装置
公开(公告)号：WO2009154692A3
公开(公告)日：2010-03-18
申请号：PCT/US2009003284
申请日：2009-05-29
申请人： VNS PORTFOLIO LLC , SANDERSON DEAN , MOORE CHARLES H , LEBERKNIGHT RANDALL , MONTVELISHSKY MICHAEL B , FOX JEFFREY A
发明人： SANDERSON DEAN , MOORE CHARLES H , LEBERKNIGHT RANDALL , MONTVELISHSKY MICHAEL B , FOX JEFFREY A
IPC分类号： G06F9/06 , G06F1/32 , G06F9/30 , G06F15/163 , G06F15/17
CPC分类号： G06F15/17 , G06F1/3203 , G06F9/3879
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a stream loader (100) which is capable of sending a stream of compiled object code to multiple computers of a multicore processor along a predefined path (84) by using execution of instructions directly from the communication ports of the computers.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入睡眠状态，直到另一台计算机（12）准备好完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）指令可以包括流加载器（100），其能够通过直接从计算机的通信端口执行指令，沿着预定义的路径（84）向多个处理器的多个计算机发送编译的目标代码流。

6. 发明申请

WO2007098005A3 MICROLOOP COMPUTER INSTRUCTIONS 审中-公开
标题翻译： MICROLOOP计算机指令
公开(公告)号：WO2007098005A3
公开(公告)日：2008-10-09
申请号：PCT/US2007004029
申请日：2007-02-16
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
发明人： MOORE CHARLES H , FOX JEFFREY ARTHUR , RIBLE JOHN W
IPC分类号： G06F7/38
CPC分类号： G06F15/8007 , G06F1/32 , G06F9/30134 , G06F9/325 , G06F9/3802 , G06F9/3885
摘要： A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise have required an interrupt of an otherwise active computer.
摘要翻译：计算机阵列（10）具有多个计算机（12）。计算机（12）以异步方式彼此通信，并且计算机（12）本身以内部的大致异步方式进行操作。当一台计算机（12）尝试与另一台计算机（12）进行通信时，它将进入休眠状态，直到另一台计算机（12）准备好完成交易，从而节省电力并减少热量产生。休眠计算机（12）可以等待数据或指令（12）。在指令的情况下，睡眠计算机（12）可以等待存储指令或者立即执行指令。在后一种情况下，在首先将指令首先置于存储器中之前，将指令置于指令寄存器（30a）中，当它们被接收和执行时，它们被放置在指令寄存器（30a）中。指令可以包括能够重复执行一系列操作的微循环（100）。在一个应用中，休眠计算机（12）被输入唤醒，使得它开始了否则将需要另外活动的计算机的中断的动作。

7. 发明申请

WO2010056369A3 METHOD AND APPARATUS FOR CIRCUIT SIMULATION 审中-公开
标题翻译：电路仿真方法与装置
公开(公告)号：WO2010056369A3
公开(公告)日：2010-09-16
申请号：PCT/US2009006149
申请日：2009-11-17
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H
发明人： MOORE CHARLES H
IPC分类号： H01L21/66 , H01L21/02
CPC分类号： G06F17/5022
摘要： A method of preparing a circuit simulator, said method comprising initializing a normalized adjusted gate voltage value. Then performing the steps of determining a normalized adjusted gate voltage datum in dependence upon the initial normalized adjusted gate voltage value. Storing the normalized adjusted gate voltage datum at a memory address in a one- dimensional array based on the normalized adjusted gate voltage. Decrementing the normalized adjusted gate voltage value by a predetermined decrement amount. And verifying the decremented gate voltage value. Then repeating until a stop gate voltage value is reached.
摘要翻译：一种制备电路模拟器的方法，所述方法包括初始化归一化的调节栅极电压值。然后根据初始归一化调整后的栅极电压值执行确定归一化的调整栅极电压数据的步骤。基于归一化的调节栅极电压将归一化的调整栅极电压基准存储在一维阵列中的存储器地址处。将归一化的调整后的栅极电压值递减预定的减量量。并验证减小的栅极电压值。然后重复，直到达到停止栅极电压值。

8. 发明申请

WO2009042107A3 SHIFT-ADD BASED PARALLEL MULTIPLICATION 审中-公开
标题翻译：基于移位补偿的并行乘法
公开(公告)号：WO2009042107A3
公开(公告)日：2010-07-01
申请号：PCT/US2008011000
申请日：2008-09-23
申请人： VNS PORTFOLIO LLC , ELLIOT GIBSON D , MOORE CHARLES H
发明人： ELLIOT GIBSON D , MOORE CHARLES H
IPC分类号： G06F7/52
CPC分类号： G06F7/582
摘要： A system for performing parallel multiplication on a plurality of factors. In a binary processor, a first and a second memory have pluralities of bit-positions. The first memory holds a first value as a multiplier that will commonly serve as multiple of the factors, and the second memory holds a second value that is representative of multiple multiplicands that are other of the factors. A multiplier bit-count is determined of the significant bits in the multiplier. And a +* operation is performed with the first value and said second value a quantity of times equaling the multiplier bit-count.
摘要翻译：一种用于对多个因素执行并行乘法的系统。在二进制处理器中，第一和第二存储器具有多个位位置。第一存储器保持第一值作为通常用作因子的倍数的乘数，并且第二存储器保存代表作为其他因素的多个被乘数的第二值。确定乘法器中有效位的乘法器位计数。并且使用第一值和所述第二值执行+ *操作等于乘数位计数的次数。

9. 发明申请

WO2009042106A3 SHIFT-ADD MECHANISM 审中-公开
标题翻译：移动机构
公开(公告)号：WO2009042106A3
公开(公告)日：2010-07-01
申请号：PCT/US2008010999
申请日：2008-09-23
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H
发明人： MOORE CHARLES H
IPC分类号： G06F7/50
CPC分类号： G06F7/582
摘要： A method to perform a shift-add operation on two values loaded in two memories of a processor where the first memory has a low bit (LB) and a high bit (HB). If the LB is zero, then this is case (1), if the HB is also zero, shifting the first value lower one bit-position and setting the HB to zero, thereby arriving at a new value in the first memory, and alternately if the HB is one, then this is case (2), and proceed shifting the first value lower one bit-position and setting the HB to one, thereby arriving at the new value. However, if the LB is one, then adding the second value to the first value in the first memory and if this does not produce a carry, proceeding as if at case (1) and otherwise proceeding as if at case (2).
摘要翻译：一种用于对第一存储器具有低位（LB）和高位（HB）的处理器的两个存储器中的两个值执行移位加法运算的方法。如果LB为零，那么这是情况（1），如果HB也为零，则将第一个值向下移动一个位位置并将HB设置为零，从而在第一个存储器中达到一个新值如果HB为1，则为情况（2），并且将第一个值向下移位一位位置并将HB设置为1，从而达到新值。然而，如果LB为1，则将第二个值添加到第一个存储器中的第一个值，并且如果不产生随机数，那么在情况（1）的情况下进行处理，否则继续进行，就像在情况（2）一样。

10. 发明申请

WO2009128920A2 MICROPROCESSOR EXTENDED INSTRUCTION SET MODE 审中-公开
标题翻译：微处理器扩展指令设置模式
公开(公告)号：WO2009128920A2
公开(公告)日：2009-10-22
申请号：PCT/US2009002357
申请日：2009-04-15
申请人： VNS PORTFOLIO LLC , MOORE CHARLES H
发明人： MOORE CHARLES H
IPC分类号： G06F9/46 , G06F12/02 , G06F13/38
CPC分类号： G11C5/025 , G11C5/02 , G11C8/14 , Y10T29/49002
摘要： Disclosed is a system and method of adding functionality to a microprocessor, especially a RISC machine having a plurality of cores, with minimal changes in circuitry and while maintaining legacy features. An enhancement to the microprocessor involves modifying a program counter register (P-register). This invention increases the number of bits in the P-register from 9 to 10. A tenth bit signals an extended instruction mode. When the tenth bit is not set, microprocessor instructions perform legacy functions. When the tenth bit is set, the extended instruction mode is active and instructions perform different or enhanced functions.
摘要翻译：公开了一种向微处理器，特别是具有多个核心的RISC机器添加功能的系统和方法，具有最小的电路变化和同时保持传统特征。对微处理器的增强涉及修改程序计数器寄存器（P寄存器）。本发明将P寄存器中的比特数从9增加到10.第10比特表示扩展指令模式。当第十位未设置时，微处理器指令执行传统功能。当第10位置1时，扩展指令模式有效，指令执行不同或增强的功能。

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