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1. 发明申请

WO2011058392A1 INTEGRATED CIRCUIT ARRANGEMENT FOR BUFFERING SERVICE REQUESTS 审中-公开
标题翻译：用于缓冲服务要求的集成电路布置
公开(公告)号：WO2011058392A1
公开(公告)日：2011-05-19
申请号：PCT/IB2009/055014
申请日：2009-11-11
申请人： VL C.V. , HENRIKSSON, Tomas , COENEN, Martijn , VAN DER WOLF, Pieter , STEFFENS, Elisabeth, Francisca, Maria
发明人： HENRIKSSON, Tomas , COENEN, Martijn , VAN DER WOLF, Pieter , STEFFENS, Elisabeth, Francisca, Maria
IPC分类号： H04L12/56 , H04L29/08
CPC分类号： H04L47/2441 , H04L47/2475 , H04L47/50 , H04L49/9063
摘要： The present invention discloses an integrated circuit arrangement (100) comprising a data communication network comprising a plurality of connections (300), a plurality of modules (110) coupled to the data communication network via at least one network interface (120), the network interface comprising a plurality of buffers; a remote service module (150) being coupled to the data communication network via a further network interface (140), wherein each of said modules (1 10) is arranged to provide its network interface (120) with a service request (200) for the remote service module (150), said network interface being arranged to extend said service request with a first identifier (204) for establishing a network connection (300) with a remote service module (150); and a circuit portion (350) comprising a plurality of buffers (142) between the at least one network interface (120) and the remote service module (150) for storing service requests (200) from the plurality of modules (110), said circuit portion comprising decoding logic (144) for selecting one of said buffers (142) by decoding a further identifier (210) embedded in the service request (200).
摘要翻译：本发明公开了一种集成电路装置（100），包括数据通信网络，该数据通信网络包括多个连接（300），经由至少一个网络接口（120）耦合到数据通信网络的多个模块（110），网络接口，包括多个缓冲器; 远程服务模块（150）经由另外的网络接口（140）耦合到数据通信网络，其中每个所述模块（110）被布置为向其网络接口（120）提供服务请求（200），用于所述远程服务模块（150），所述网络接口被布置为利用用于与远程服务模块（150）建立网络连接（300）的第一标识符（204）来扩展所述服务请求; 以及电路部分（350），包括在所述至少一个网络接口（120）和所述远程服务模块（150）之间的多个缓冲器（142），用于从所述多个模块（110）存储服务请求（200），所述电路部分包括用于通过解码嵌入在服务请求（200）中的另外的标识符（210）来选择所述缓冲器（142）之一的解码逻辑（144）。

2. 发明申请

WO2010018494A1 IMAGE COMPRESSION 审中-公开
标题翻译：图像压缩
公开(公告)号：WO2010018494A1
公开(公告)日：2010-02-18
申请号：PCT/IB2009/053431
申请日：2009-08-06
申请人： NXP B.V. , LI, Shuo , RIEMENS,, Abraham Karel , HENRIKSSON, Tomas , VAN DER WOLF, Pieter
发明人： LI, Shuo , RIEMENS,, Abraham Karel , HENRIKSSON, Tomas , VAN DER WOLF, Pieter
IPC分类号： G06T9/00 , H04N7/32 , H04N7/26 , H04N1/64
CPC分类号： H04N1/644 , H04N19/11 , H04N19/172 , H04N19/182 , H04N19/593 , H04N19/91
摘要： An image compression unit for compressing image data (ID) having a plurality of pixels, each with one or more color samples, into a compressed format (CF) is provided. The image compression unit comprises a color lookup table generation unit (311) for generating a color lookup table having one or more colors and for transmitting the color lookup table in the compressed format (CF). The image compression unit further comprises a pixel mode determination unit (312) for determining for at least one pixel of the image data (ID) a pixel mode and for transmitting for the at least one pixel a pixel mode identifier for identifying the pixel mode in the compressed format (CF). A first pixel mode corresponds to the case that the at least one pixel matches one of the one or more colors in the color lookup table and a second pixel mode corresponds to the case that the at least one pixel does not match one of the one or more colors in the color lookup table. The image compression unit further comprises a color lookup table encoding unit (313) for encoding pixels whose pixel mode is the first pixel mode and a predictive encoding unit (314) for predictively encoding pixels whose pixel mode is the second pixel mode.
摘要翻译：提供一种图像压缩单元，用于将具有多个像素的图像数据（ID）分别压缩成压缩格式（CF），每个像素具有一个或多个颜色样本。图像压缩单元包括用于生成具有一种或多种颜色并用于以压缩格式（CF）发送颜色查找表的颜色查找表的颜色查找表生成单元。图像压缩单元还包括像素模式确定单元（312），用于为像素模式中的图像数据（ID）的至少一个像素确定像素模式，并且为至少一个像素发送用于识别像素模式的像素模式标识符压缩格式（CF）。第一像素模式对应于至少一个像素匹配颜色查找表中的一种或多种颜色之一的情况，而第二像素模式对应于至少一个像素不匹配一个或多个颜色之一的情况在颜色查找表中有更多的颜色。图像压缩单元还包括用于编码其像素模式是第一像素模式的像素的颜色查找表编码单元（313）和用于预测编码其像素模式是第二像素模式的像素的预测编码单元（314）。

3. 发明申请

WO2010055494A1 A CACHE MANAGEMENT POLICY AND CORRESPONDING DEVICE 审中-公开
标题翻译：高速缓存管理政策及相关设备
公开(公告)号：WO2010055494A1
公开(公告)日：2010-05-20
申请号：PCT/IB2009/055080
申请日：2009-11-16
申请人： NXP B.V. , VAN DER WOLF, Pieter , RIEMENS, Abraham Karel , VAN DE WAERDT, Jan-Willem
发明人： VAN DER WOLF, Pieter , RIEMENS, Abraham Karel , VAN DE WAERDT, Jan-Willem
IPC分类号： G06F12/08
CPC分类号： G06F12/0804 , G06F2212/1044
摘要： A cache management policy is provided, comprising a method for writing back to a memory (104) a data element set (122) stored in a cache (110). The method reduces the time some items stay in the cache, and thereby improves the utilization of the cache for some applications, especially for video applications. The method comprises determining that each one of the multiple data elements has been updated through at least one write request; marking the data element set as a write-back candidate, in dependency on said determination; and writing the write-back candidate to the memory.
摘要翻译：提供了一种缓存管理策略，包括用于将存储在高速缓存（110）中的数据元素集（122）的存储器（104）写回的方法。该方法减少了某些项目停留在缓存中的时间，从而提高了某些应用程序的缓存的利用率，特别是对于视频应用程序。该方法包括通过至少一个写入请求确定多个数据元素中的每一个已被更新; 根据所述确定将数据元素标记为回写候选者; 并将写回候选者写入存储器。

4. 发明申请

WO2003005731A1 MOTION ESTIMATION AND COMPENSATION WITH CONTROLLED VECTOR STATISTICS 审中-公开
标题翻译：运动估计和补偿与控制矢量统计
公开(公告)号：WO2003005731A1
公开(公告)日：2003-01-16
申请号：PCT/IB2002/002420
申请日：2002-06-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SCHUTTEN, Robert, J. , RIEMENS, Abraham, K. , VAN DER WOLF, Pieter
发明人： SCHUTTEN, Robert, J. , RIEMENS, Abraham, K. , VAN DER WOLF, Pieter
IPC分类号： H04N7/34
CPC分类号： H04N19/433 , H04N19/51
摘要： Method and system for motion compensation in video image data, comprising a motion estimator (12) arranged for analysing motion in consecutive frames of the video image data and deriving a motion vector field in dependence on said motion, a motion compensator (14) connected to the motion estimator (12) and first storage means (15). The motion compensator (14) is arranged for performing motion compensation by storing a subset of the video image data in a first storage means (15) and, for each vector retrieving the required data from the first storage means (15), where in cases that the required data is not entirely available in the first storage means (15), video image data containing at least the missing parts of the required data, is retrieved from a second storage means (10) and stored in the first storage means (15). The motion estimator (12) is further arranged to select motion vectors in the video motion vector field which meet at least one statistical property.
摘要翻译：一种视频图像数据中的运动补偿方法和系统，包括：运动估计器（12），用于分析视频图像数据的连续帧中的运动并根据所述运动导出运动矢量场;运动补偿器（14），连接到运动估计器（12）和第一存储装置（15）。运动补偿器（14）被布置为通过将视频图像数据的子集存储在第一存储装置（15）中并且对于从第一存储装置（15）检索所需数据的每个向量来执行运动补偿，其中在情况下在第一存储装置（15）中所需数据不完全可用，至少包含所需数据的缺失部分的视频图像数据从第二存储装置（10）检索并存储在第一存储装置（15）中）。运动估计器（12）还被布置成选择满足至少一个统计特性的视频运动矢量场中的运动矢量。

5. 发明申请

WO2005088982A1 VIDEO PROCESSING CIRCUIT AND METHOD OF VIDEO PROCESSING 审中-公开
标题翻译：视频处理电路和视频处理方法
公开(公告)号：WO2005088982A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050702
申请日：2005-02-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DER WOLF, Pieter , RIEMENS, Abraham, K. , GANGWAL, Om, P.
发明人： VAN DER WOLF, Pieter , RIEMENS, Abraham, K. , GANGWAL, Om, P.
IPC分类号： H04N7/50
CPC分类号： H04N19/85 , H04N19/159 , H04N19/423 , H04N19/44 , H04N19/61
摘要： Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory (12, 106) respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.
摘要翻译：诸如包括MPEG解码后续后处理的视频流处理涉及使用信号处理电路（102,106）来执行第一和第二视频流处理功能。第一视频流处理功能在时间有序的输出帧序列中产生连续视频帧的帧数据。第二视频流处理功能使用与输出序列不同的帧的有序输入序列中的帧数据，例如因为需要稍后的P帧来解码B帧。帧数据在第一和第二视频处理功能的应用与帧数据之间被缓冲。第一和第二。使用缓冲存储器（12,106）。第一缓冲存储器（12）经由诸如外部IC端子之类的共享通道（15）耦合到信号处理电路，但处理电路不使用可共享通道（15）访问第二缓冲存储器（106）。第二视频处理功能分别从第一和第二缓冲存储器（12,106）中选择性地从第一和第二帧中读取帧数据。帧中的第二帧在输入和输出序列中以相同的时间顺序发生。帧中的第一帧包含至少所有特定帧，其相对于输出序列中的第二帧的位置与特定帧相对于输入序列中的第二帧的位置不同。

6. 发明申请

WO2005085994A2 MULTI-TASKING DATA PROCESSING SYSTEM 审中-公开
标题翻译：多任务数据处理系统
公开(公告)号：WO2005085994A2
公开(公告)日：2005-09-15
申请号：PCT/IB2005/050624
申请日：2005-02-21
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ESSINK, Gerben , KANG, I-Chih , VAN DER WOLF, Pieter
发明人： ESSINK, Gerben , KANG, I-Chih , VAN DER WOLF, Pieter
IPC分类号： G06F9/40
CPC分类号： G06F9/485 , G06F9/4881
摘要： The invention provides a data processing system which has a reduced multitasking overhead. The invention relies on the perception that unnecessary task interruptions can be avoided if a current task can determine whether another task will be executed after the current task's interruption. If the current task can retrieve information about the next task to be executed, it can determine whether its interruption is justified or not. In particular, if the scheduling unit reschedules the current task for immediate execution (i.e. without scheduling another task to execute first), then the interruption is unnecessary. In that case, the current task should simply proceed with its execution. If another task has indeed been scheduled, then the current task should indeed interrupt its execution and return control to the scheduling unit.
摘要翻译：本发明提供了具有减少的多任务开销的数据处理系统。本发明依赖于如果当前任务可以确定在当前任务中断之后是否执行另一个任务，那么可以避免不必要的任务中断。如果当前任务可以检索有关待执行的下一个任务的信息，则可以确定其中断是否为正确。特别地，如果调度单元重新调度当前任务以立即执行（即，不调度另一任务以首先执行），则不需要中断。在这种情况下，当前任务应该直接执行。如果确实已经安排了另一个任务，那么当前任务应该确实中断其执行并将控制权返回给调度单元。

7. 发明申请

WO2005026964A2 DATA PROCESSING SYSTEM 审中-公开
标题翻译：数据处理系统
公开(公告)号：WO2005026964A2
公开(公告)日：2005-03-24
申请号：PCT/IB2004/051491
申请日：2004-08-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DER WOLF, Pieter , VAN EIJNDHOVEN, Josephus, T., J. , BOONSTRA, Johannes
发明人： VAN DER WOLF, Pieter , VAN EIJNDHOVEN, Josephus, T., J. , BOONSTRA, Johannes
IPC分类号： G06F12/08
CPC分类号： G06F13/1663 , G06F12/0831
摘要： The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H 11, H 12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
摘要翻译：所公开的数据处理系统包括存储装置（SDRAM），提供用于访问所述存储装置（SDRAM）的多个数据处理装置（IP）以及耦合在所述存储装置（SDRAM）和所述多个数据处理装置（IP），所述通信接口装置包括节点网络（H 11，H 12，H 2），每个节点包括用于从数据处理装置（IP）接收存储器访问请求的至少一个从端口）或来自前一节点的至少一个主端口（m），用于根据在所述从端口处接收到的存储器访问请求向下一个节点或所述存储器装置（SDRAM）发出存储器访问请求，其中所述至少一个从属端口连接到先前节点的主端口（m）或所述数据处理装置（IP）中的一个，并且所述至少一个主端口（m）连接到从端口 s）或所述存储装置（SDRAM）。

8. 发明申请

WO2007135602A1 ELECTRONIC DEVICE AND METHOD FOR STORING AND RETRIEVING DATA 审中-公开
标题翻译：用于存储和检索数据的电子设备和方法
公开(公告)号：WO2007135602A1
公开(公告)日：2007-11-29
申请号：PCT/IB2007/051783
申请日：2007-05-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RIEMENS, Abraham, K. , VAN DER WOLF, Pieter , VAN DER VLEUTEN, Renatus, J.
发明人： RIEMENS, Abraham, K. , VAN DER WOLF, Pieter , VAN DER VLEUTEN, Renatus, J.
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G06F12/023 , G06F2212/401 , H04N19/426
摘要： A data processing device is provided, which comprises at least one processing unit (IP) for processing data based on a logical address space (LAS); and a communication infrastructure (B) comprising an interconnect (B) for communicating data and addresses between the at least one processing unit (IP) and a memory unit (MU) storing compressed and/or uncompressed data based on a physical address space (PAS). The data processing device further comprises a compression unit (CU) for compressing data and/or for decompressing compressed data. Moreover, a transformation unit (TU) is provided for performing an address transformation between the logical address space (LAS) and the physical address space (PAS) of an address associated with the data compressed and/or decompressed by the compression unit (CU). The size of the compressed data in the physical address space (PAS) is smaller than the size of the corresponding uncompressed data in the logical address space (LAS).
摘要翻译：提供一种数据处理装置，其包括用于基于逻辑地址空间（LAS）处理数据的至少一个处理单元（IP）; 以及通信基础设施（B），其包括用于在所述至少一个处理单元（IP）和存储单元（MU）之间传送数据和地址的互连（B），所述存储单元（MU）基于物理地址空间（PAS）存储压缩和/或未压缩数据）。数据处理装置还包括用于压缩数据和/或解压缩压缩数据的压缩单元（CU）。此外，提供变换单元（TU），用于在与由压缩单元（CU）压缩和/或解压缩的数据相关联的地址的逻辑地址空间（LAS）和物理地址空间（PAS）之间进行地址变换，。物理地址空间（PAS）中的压缩数据的大小小于逻辑地址空间（LAS）中对应的未压缩数据的大小。

9. 发明申请

WO2004092960A2 DATA PROCESSING APPARATUS THAT USES COMPRESSION FOR DATA STORED IN MEMORY 审中-公开
标题翻译：使用存储器中存储的数据进行压缩的数据处理设备
公开(公告)号：WO2004092960A2
公开(公告)日：2004-10-28
申请号：PCT/IB2004/050426
申请日：2004-04-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RIEMENS, Abraham, K. , VAN DER VLEUTEN, Renatus, J. , VAN DER WOLF, Pieter
发明人： RIEMENS, Abraham, K. , VAN DER VLEUTEN, Renatus, J. , VAN DER WOLF, Pieter
IPC分类号： G06F12/08
CPC分类号： G06F12/08 , G06F12/02 , G06F12/0802 , G06F2212/1041 , G06F2212/401 , H03M7/30
摘要： Data, such as an image, is made up of data-items (pixels) that are each associated with a respective data address. Compressed blocks representing the data are stored in a memory system. Each block representing compressed data-items associated with data addresses in a respective sub-range of addresses of the data. Each block starts from a respective preferred starting address for multi address transfer. The sub-range of addresses of each block has a length corresponding to an address distance between the preferred starting address, leaving memory addresses not occupied by the particular block in between blocks due to compression. A decompressor is coupled between a processing element and the memory system. The decompressor starts a multi address memory transfer of a required one of the blocks from the memory system dynamically when the processing element requires access to the block, leaving memory addresses directly following the block up to a preferred starting address for a next one of the blocks untransferred in the transfer. The transferred data is decompressed and passed to the processor.
摘要翻译：诸如图像的数据由每个与相应数据地址相关联的数据项（像素）组成。表示数据的压缩块存储在存储器系统中。每个块表示与数据的地址的相应子范围中的数据地址相关联的压缩数据项。每个块从相应的优选起始地址开始，用于多地址传送。每个块的地址子范围具有对应于优选起始地址之间的地址距离的长度，留下由于压缩而不在块之间的特定块的存储器地址。解压缩器耦合在处理元件和存储器系统之间。当处理元件需要访问该块时，解压缩器动态地从存储器系统中开始对存储器系统中所需的一个块的多地址存储器传输，使存储器地址直接跟随块直到下一个块的优选起始地址未转让转让。传输的数据被解压缩并传递给处理器。

10. 发明申请

WO2003052586A3 DATA PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS 审中-公开
公开(公告)号：WO2003052586A3
公开(公告)日：2003-06-26
申请号：PCT/IB2002/005168
申请日：2002-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J. , RUTTEN, Martijn, J. , VAN DER WOLF, Pieter , GANGWAL, Om, P.
发明人： VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J. , RUTTEN, Martijn, J. , VAN DER WOLF, Pieter , GANGWAL, Om, P.
IPC分类号： G06F9/46
摘要： The invention is based on the idea to effectively separate communication hardware, e.g. busses and memory, and computation hardware, e.g. processors, in a data processing system by introducing a communication means for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication means provide the communication support for the respective processor. Therefore, a data processing system is provided with a computation, a communication support and a communication network layer. The computation layer comprises a first and at least a second processor for processing a stream of data objects. The first processor passes a number of data objects from a stream to the second processor which can then process the data objects. The communication network layer includes a memory and a communication network for linking the first processor and the second processors with said memory. The communication support layer is arranged between the computation layer and the communication network layer and comprises one communication means for each second processor in the computation layer. The communication means of each of the second processors controls the communication between the said second processor and the memory via the communication network in the communication network layer.

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