专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006082554A3 DATA PROCESSING SYSTEM COMPRISING A CACHE UNIT 审中-公开
标题翻译：包含高速缓存单元的数据处理系统
公开(公告)号：WO2006082554A3
公开(公告)日：2006-10-12
申请号：PCT/IB2006050319
申请日：2006-01-30
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN EIJNDHOVEN JOSEPHUS T J , STRAVERS PAUL , MOLNOS ANCA M
发明人： VAN EIJNDHOVEN JOSEPHUS T J , STRAVERS PAUL , MOLNOS ANCA M
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0864 , G06F12/084 , G06F12/0848
摘要： The invention implements a cache partitioning technique that operates on cache sets. As caches typically have many sets (such as several hundreds), set partitioning can provide the granularity to control many individual objects. The problem with conventional caches is that the sets are selected by direct addressing. This selection must be unique and uniform, otherwise different processes cannot access each others shared data. The proposed solution adopts a lookup-table that can contain a generic set selection function, and that is integrated close to the cache itself to provide a single global mapping shared between all processes and processors, and that can operate at the speed of the cache itself.
摘要翻译：本发明实现了对缓存集进行操作的缓存分区技术。由于缓存通常具有许多组（例如几百个），所以设置分区可以提供粒度来控制许多单独的对象。常规高速缓存的问题是这些集合是通过直接寻址选择的。这个选择必须是唯一的和统一的，否则不同的进程不能访问彼此共享的数据。建议的解决方案采用查找表，该查找表可以包含通用集合选择函数，并且集成在缓存本身附近，以提供在所有进程和处理器之间共享的单个全局映射，并且可以以缓存本身的速度运行。

2. 发明申请

WO2004079488A3 DATA PROCESSING SYSTEM WITH CACHE OPTIMISED FOR PROCESSING DATAFLOW APPLICATIONS 审中-公开
标题翻译：具有优化处理数据流应用的缓存的数据处理系统
公开(公告)号：WO2004079488A3
公开(公告)日：2005-07-28
申请号：PCT/IB2004050150
申请日：2004-02-25
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
发明人： VAN EIJNDHOVEN JOSEPHUS T J , RUTTEN MARTIJN J , POL EVERT-JAN D
IPC分类号： G06F12/08
CPC分类号： G06F12/084
摘要： Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises selecting means (350) for selecting locations for storing elements of a data stream in said cache memory (200) in accordance to said stream identification (stream_id).
摘要翻译：为每个数据流保留非重叠缓存位置。因此，每个流唯一的流信息用于对高速缓冲存储器进行索引。这里，流信息由流标识表示。特别地，提供了优化用于处理具有任务和数据流的数据流应用的数据处理系统，其中不同流竞争共享高速缓存资源。明确的流识别与每个所述数据流相关联。所述数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个所述处理器）和用于控制所述高速缓冲存储器（200）的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓存存储器（200）中的每一个相关联。所述缓存控制器（300）包括选择装置（350），用于根据所述流标识（stream_id）选择用于存储所述高速缓冲存储器（200）中的数据流元素的位置。

3. 发明申请

WO2004017641A8 A METHOD OF COMMUNICATING DATA WITHIN A CODER 审中-公开
标题翻译：在编码器中传送数据的方法
公开(公告)号：WO2004017641A8
公开(公告)日：2005-03-17
申请号：PCT/IB0303254
申请日：2003-07-16
申请人： KONINKL PHILIPS ELECTRONICS NV , VAN DER TOL ERIK B , HEKSTRA GERBEN J , POL EVERT-JAN D , VAN EIJNDHOVEN JOSEPHUS T J
发明人： VAN DER TOL ERIK B , HEKSTRA GERBEN J , POL EVERT-JAN D , VAN EIJNDHOVEN JOSEPHUS T J
IPC分类号： H03M7/30 , H04N7/26 , H04N7/30 , H04N7/50
CPC分类号： H04N19/423 , H04N19/60 , H04N19/61
摘要： Transform based coders are frequently used in digital signal processing. The present invention relates to a method of communicating at least one block of data from a first functional element (3; 4; 7; 12; 14) within a transform based coder (1) or decoder (10) to a second functional element (4; 5; 7; 8; 14; 15) within the coder or decoder, where the block of data comprises a row-column structure of data coefficients. A significant communication workload occurs between individual elements of the coders and decoders. The present invention seeks to reduce this workload by making an effort to communicate only non-zero coefficients within a cartesian bounding box of a block between various functional units in a decoding or encoding scheme by reducing the size of the at least one block of data to produce a reduced size data block by elimination (31) of one or more rows and/or columns of substantially zero valued coefficients, and communicating (32) the reduced size data block from the first functional element to the second functional element.
摘要翻译：基于变换的编码器经常用于数字信号处理。本发明涉及一种将至少一个数据块从基于变换的编码器（1）或解码器（10）内的第一功能元件（3; 4; 7; 12; 14）传送到第二功能元件 4; 5; 7; 8; 14; 15），其中数据块包括数据系数的行列结构。在编码器和解码器的各个元件之间发生重大的通信工作。本发明寻求通过将解码或编码方案中的各个功能单元之间的块的笛卡尔边界框内的非零系数通过将至少一个数据块的大小减小到通过消除（31）基本上零值系数的一个或多个行和/或列，并且将缩小尺寸的数据块从第一功能元件传送到第二功能元件，从而产生缩小尺寸的数据块。

4. 发明申请

WO2004017641A1 A METHOD OF COMMUNICATING DATA WITHIN A CODER 审中-公开
标题翻译：在编码器中传送数据的方法
公开(公告)号：WO2004017641A1
公开(公告)日：2004-02-26
申请号：PCT/IB2003/003254
申请日：2003-07-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DER TOL, Erik, B. , HEKSTRA, Gerben, J. , POL, Evert-Jan, D. , VAN EIJNDHOVEN, Josephus, T., J.
发明人： VAN DER TOL, Erik, B. , HEKSTRA, Gerben, J. , POL, Evert-Jan, D. , VAN EIJNDHOVEN, Josephus, T., J.
IPC分类号： H04N7/50
CPC分类号： H04N19/423 , H04N19/60 , H04N19/61
摘要： Transform based coders are frequently used in digital signal processing. The present invention relates to a method of communicating at least one block of data from a first functional element (3; 4; 7; 12; 14) within a transform based coder (1) or decoder (10) to a second functional element (4; 5; 7; 8; 14; 15) within the coder or decoder, where the block of data comprises a row-column structure of data coefficients. A significant communication workload occurs between individual elements of the coders and decoders. The present invention seeks to reduce this workload by making an effort to communicate only non-zero coefficients within a cartesian bounding box of a block between various functional units in a decoding or encoding scheme by reducing the size of the at least one block of data to produce a reduced size data block by elimination (31) of one or more rows and/or columns of substantially zero valued coefficients, and communicating (32) the reduced size data block from the first functional element to the second functional element.
摘要翻译：基于变换的编码器经常用于数字信号处理。本发明涉及一种将至少一个数据块从基于变换的编码器（1）或解码器（10）内的第一功能元件（3; 4; 7; 12; 14）传送到第二功能元件 4; 5; 7; 8; 14; 15），其中数据块包括数据系数的行列结构。在编码器和解码器的各个元件之间发生重大的通信工作。本发明寻求通过将解码或编码方案中的各个功能单元之间的块的笛卡尔边界框内的非零系数通过将至少一个数据块的大小减小到通过消除（31）基本上零值系数的一个或多个行和/或列，并且将缩小尺寸的数据块从第一功能元件传送到第二功能元件，从而产生缩小尺寸的数据块。

5. 发明申请

WO2003052597A3 DATA PROCESSING SYSTEM HAVING MULTIPLE PROCESSORS AND TASK SCHEDULER AND CORRESPONDING METHOD THEREFORE 审中-公开
公开(公告)号：WO2003052597A3
公开(公告)日：2003-06-26
申请号：PCT/IB2002/005199
申请日：2002-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RUTTEN, Martijn, J. , VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J.
发明人： RUTTEN, Martijn, J. , VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J.
IPC分类号： G06F9/46
摘要： The invention is based on the idea to provide distributed task scheduling in a data processing system having multiple processors. Therefore, a data processing system comprising a first and at least one second processor for processing a stream of data objects, wherein said first processor passes data objects from a stream of data objects to the second processor, and a communication network and a memory is provided. Said second processors are multi-tasking processors, capable of interleaved processing of a first and second task, wherein said first and second tasks process a first and second stream of data objects, respectively. Said data processing system further comprises a task scheduling means for each of said second processors, wherein said task scheduling means is operatively arranged between said second processor and said communication network, and controls the task scheduling of said second processor.

6. 发明申请

WO2003052589A2 METHOD FOR DATA PROCESSING IN A MULTI-PROCESSOR DATA PROCESSING SYSTEM AND A CORRESPONDING DATA PROCESSING SYSTEM 审中-公开
标题翻译：多处理器数据处理系统中的数据处理方法和相应的数据处理系统
公开(公告)号：WO2003052589A2
公开(公告)日：2003-06-26
申请号：PCT/IB2002/005244
申请日：2002-12-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J. , RUTTEN, Martijn, J.
发明人： VAN EIJNDHOVEN, Josephus, T., J. , POL, Evert, J. , RUTTEN, Martijn, J.
IPC分类号： G06F9/00
CPC分类号： G06F9/30087
摘要： The invention is based on the idea to separate a synchronisation operation from reading and writing operations. Therefore, a method for data processing in the data processing system is provided, wherein said data processing system comprises a first and at least a second processor for processing streams of data objects, wherein said first processor passes data objects from a stream of data objects to the second processor. Said data processing system further comprises at least one memory for storing and retrieving data objects, wherein a shared access of said first and second processors is provided. The processors perform a read operations and/or write operations in order to exchange data objects with his said memory. Said processors further perform inquiry operations and/or commit operations in order to synchronise a data object transfer between tasks which are executed by said processors. Said inquiry operations and said commit operations are performed independently of said read operations and said write operations by said processors.
摘要翻译：本发明基于将同步操作与读写操作分开的思想。因此，提供了一种数据处理系统中的数据处理方法，其中所述数据处理系统包括用于处理数据对象流的第一和至少第二处理器，其中所述第一处理器将数据对象从数据对象流传递到第二个处理器。所述数据处理系统还包括用于存储和检索数据对象的至少一个存储器，其中提供所述第一和第二处理器的共享访问。处理器执行读操作和/或写操作，以便与他的所述存储器交换数据对象。所述处理器进一步执行查询操作和/或提交操作，以便同步由所述处理器执行的任务之间的数据对象传送。所述查询操作和所述提交操作独立于所述读取操作和所述处理器的所述写入操作执行。

7. 发明申请

WO2005041056A2 INTEGRATED CIRCUIT COMPRISING A MEASUREMENT UNIT FOR MEASURING UTILIZATION 审中-公开
标题翻译：包含用于测量使用的测量单元的集成电路
公开(公告)号：WO2005041056A2
公开(公告)日：2005-05-06
申请号：PCT/IB2004/052149
申请日：2004-10-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RIEMENS, Abraham, K. , VAN EIJNDHOVEN, Josephus, T., J.
发明人： RIEMENS, Abraham, K. , VAN EIJNDHOVEN, Josephus, T., J.
IPC分类号： G06F15/80
CPC分类号： G06F11/349
摘要： The invention provides an integrated circuit comprising a data processing system which performs satisfactorily after integration of the individual building blocks, such as main processors and coprocessors, into the data processing system. This is achieved by measuring the utilization of the communication structure established between the individual building blocks. A measurement unit measures properties of the communication load by observing the communication traffic on connections between processing units and a communication resource, or on connections within the communication resource. The measurement unit performs statistical operations on the observed properties and produces measurement results. The measurement results can be retrieved by measurement software and can be used to modify the data processing system, for example by debugging or by adaptive control.
摘要翻译：本发明提供了一种集成电路，其包括在将诸如主处理器和协处理器的各个构建块集成到数据处理系统中之后令人满意地执行的数据处理系统。这是通过测量在各个构建块之间建立的通信结构的利用来实现的。测量单元通过观察处理单元和通信资源之间的连接上的通信流量，或通信资源内的连接来测量通信负载的属性。测量单元对观察到的属性执行统计运算，并产生测量结果。测量结果可以通过测量软件进行检索，可以通过调试或通过自适应控制来修改数据处理系统。

8. 发明申请

WO2004079488A2 DATA PROCESSING SYSTEM WITH CACHE OPTIMISED FOR PROCESSING DATAFLOW APPLICATIONS 审中-公开
标题翻译：具有优化处理数据流应用的缓存的数据处理系统
公开(公告)号：WO2004079488A2
公开(公告)日：2004-09-16
申请号：PCT/IB2004/050150
申请日：2004-02-25
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN EIJNDHOVEN, Josephus, T., J. , RUTTEN, Martijn, J. , POL, Evert-Jan, D.
发明人： VAN EIJNDHOVEN, Josephus, T., J. , RUTTEN, Martijn, J. , POL, Evert-Jan, D.
IPC分类号： G06F
CPC分类号： G06F12/084
摘要： Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises selecting means (350) for selecting locations for storing elements of a data stream in said cache memory (200) in accordance to said stream identification (stream_id).
摘要翻译：为每个数据流保留非重叠缓存位置。因此，每个流唯一的流信息用于对高速缓冲存储器进行索引。这里，流信息由流标识表示。特别地，提供了优化用于处理具有任务和数据流的数据流应用的数据处理系统，其中不同流竞争共享高速缓存资源。明确的流识别与每个所述数据流相关联。所述数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个所述处理器）和用于控制所述高速缓冲存储器（200）的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓冲存储器（200）中的每一个相关联。所述高速缓存控制器（300）包括选择装置（350），用于根据所述流标识（stream_id）选择用于存储所述高速缓冲存储器（200）中的数据流元素的位置。

9. 发明申请

WO2004077206A2 DATA PROCESSING SYSTEM HAVING A PLURALITY OF PROCESSING ELEMENTS, A METHOD OF CONTROLLING A DATA PROCESSING SYSTEM HAVING A PLURALITY OF PROCESSING ELEMENTS 审中-公开
标题翻译：具有多种加工元素的数据处理系统，一种控制具有多种加工元素的数据处理系统的方法
公开(公告)号：WO2004077206A2
公开(公告)日：2004-09-10
申请号：PCT/IB2004050124
申请日：2004-02-18
申请人： KONINKL PHILIPS ELECTRONICS NV , RUTTEN MARTIJN J , VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT-JAN D
发明人： RUTTEN MARTIJN J , VAN EIJNDHOVEN JOSEPHUS T J , POL EVERT-JAN D
IPC分类号： G06F1/00 , G06F9/44 , G06F9/46 , G06F
CPC分类号： G06F9/4436 , G06F9/52
摘要： The invention relates to task management in a data processing system, having a plurality of processing elements (CPU, ProcA, ProcB, ProcC). Therefore a data processing system is provided, comprising at least a first processing element (CPU, ProcA, ProcB, ProcC) and a second processing element (CPU, ProcA, ProcB, ProcC) for processing a stream of data objects (DS_Q, DS R, DS S, DST), the first processing element being arranged to pass data objects from the stream of data objects to the second processing element. The first and the second processing element are arranged for parallel execution of an application comprising a set of tasks (TP, TA, TB 1, TB2, TC), and the first and the second processing element are arranged to be responsive to the receipt of a unique identifier. In order to ensure integrity of data during reconfiguration of the application, the unique identifier is inserted into the data stream and passed from one processing element to the other. Application reconfiguration is performed when the corresponding processing element receives the unique identifier, and as a result global application control is allowed at a unique location in the data space.
摘要翻译：本发明涉及具有多个处理元件（CPU，ProcA，ProcB，ProcC）的数据处理系统中的任务管理。因此，提供了一种数据处理系统，其至少包括用于处理数据对象流（DS_Q，DSR）的至少第一处理元件（CPU，ProcA，ProcB，ProcC）和第二处理元件（CPU，ProcA，ProcB，ProcC），DS S，DST），第一处理元件被布置成将数据对象从数据对象流传递到第二处理元件。第一处理单元和第二处理单元被布置为用于并行执行包括一组任务（TP，TA，TB1，TB2，TC）的应用，并且第一和第二处理单元被布置成响应于唯一标识符。为了确保在重新配置应用期间数据的完整性，将唯一标识符插入到数据流中，并从一个处理元件传递到另一个处理元件。当对应的处理单元接收到唯一标识符时执行应用重新配置，从而在数据空间中的唯一位置允许全局应用控制。

10. 发明申请

WO2004031962A2 DATA PROCESSING SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开
标题翻译：数据处理系统及其操作方法
公开(公告)号：WO2004031962A2
公开(公告)日：2004-04-15
申请号：PCT/IB2003/004329
申请日：2003-10-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN EIJNDHOVEN, Josephus, T., J.
发明人： VAN EIJNDHOVEN, Josephus, T., J.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and a lower ranked cache (C2) is coupled to the higher ranked cache (C1) having a cache controller (CC2). The size of the higher ranked cache is smaller than the size of the lower ranked cache. Both caches (C1, C2) administrate auxiliary information (V1, V2) indicating whether data (D1, D2) present therein is valid. The linesize of the lower ranked cache (C2) is an integer multiple of the linesize of the higher ranked cache (C1). The auxiliary information (V1) in the higher ranked cache (C1) concerns data elements (D1) at a finer granularity than that in the lower ranked cache (C2). The higher ranked cache (C1) is arranged for transmitting a writemask (WM) to the lower ranked cache (C2) in conjunction with a line of data (DL) for indicating which data in the lower ranked cache (C2) is to be overwritten at the finer granularity. Fetching a line from the next lower ranked level (M) is suppressed if the writemask (WM) indicates that the line (DL) provided by the higher ranked cache (C1) is entirely valid in which case, the controller (CC2) of the lower ranked cache allocates the cache line in the lower ranked cache (C2) without fetching it.
摘要翻译：根据本发明的数据处理系统包括处理器（P）和存储器层级。其中最高排名的级别是耦合到处理器的高速缓存。存储器层级包括具有根据写分配方案操作的高速缓存控制器（CC1）的较高等级的高速缓存（C1），并且较低等级的高速缓存（C2）耦合到具有高速缓存控制器（CC2）的较高等级的高速缓存（C1））。较高排名的缓存的大小小于较低排名的高速缓存的大小。两个高速缓存（C1，C2）管理表示其中存在的数据（D1，D2）是否有效的辅助信息（V1，V2）。较低等级的高速缓存（C2）的线性化是较高等级的高速缓存（C1）的线性化的整数倍。较高等级的高速缓存（C1）中的辅助信息（V1）以比较低等级的高速缓存（C2）更细的粒度关系数据元素（D1）。排列较高的高速缓存（C1）被配置用于结合用于指示下划分的高速缓冲存储器（C2）中的哪个数据被覆盖的数据行（DL）向低分级高速缓冲存储器（C2）发送写入掩码（WM）在更细的粒度。如果写入掩码（WM）指示由较高等级的高速缓存（C1）提供的行（DL）完全有效，则在下一个较低等级（M）中获取一行，在这种情况下，控制器（CC2）较低排名的高速缓存在较低等级的高速缓存（C2）中分配高速缓存行，而不会取回它。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式