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    • 1. 发明申请
    • COMBINING A COARSE ADC AND A SAR ADC
    • 组合一个COARSE ADC和一个SAR ADC
    • WO2015103425A1
    • 2015-07-09
    • PCT/US2014/073062
    • 2014-12-31
    • TEXAS INSTRUMENTS INCORPORATEDTEXAS INSTRUMENTS JAPAN LIMITED
    • NARAYAN, Subramanian, JagdishKANNAN, Anand
    • H03M1/38
    • H03M1/144H03M1/0604H03M1/0695H03M1/468
    • In described examples, a successive approximation register analog to digital converter (SAR ADC) receives an input voltage (102) and multiple reference voltages (105). The SARADC (100) includes a charge sharing DAC (110). The charge sharing DAC (110) includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector (116) is coupled to the charge sharing DAC (110). The zero crossing detector (116) generates a digital output ( 118). A coarse ADC ( 122) receives the input voltage ( 102) and generates a coarse output (124). A predefined offset is added to a residue of the coarse ADC (122). A successive approximation register (SAR) state machine (120) is coupled to the coarse ADC (122) and the zero crossing detector (116) and generates multiple control signals (126). The control signals (126) operate the charge sharing DAC (110) in a sampling mode, an error-correction mode and a conversion mode.
    • 在所描述的示例中,逐次逼近寄存器模数转换器(SAR ADC)接收输入电压(102)和多个参考电压(105)。 SARADC(100)包括电荷共享DAC(110)。 电荷共享DAC(110)包括MSB(最高有效位)电容器阵列和LSB(最低有效位)电容器阵列。 零交叉检测器(116)耦合到电荷共享DAC(110)。 过零检测器(116)产生数字输出(118)。 粗略ADC(122)接收输入电压(102)并产生粗略输出(124)。 将预定义的偏移量添加到粗略ADC(122)的残差。 逐次逼近寄存器(SAR)状态机(120)耦合到粗略ADC(122)和过零检测器(116)并产生多个控制信号(126)。 控制信号(126)以采样模式,纠错模式和转换模式操作电荷共享DAC(110)。