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1. 发明申请

WO2008079661A1 LATCHED COMPARATOR AND METHODS FOR USING SUCH 审中-公开
标题翻译：锁定比较器和使用这种方法
公开(公告)号：WO2008079661A1
公开(公告)日：2008-07-03
申请号：PCT/US2007/087081
申请日：2007-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED , PAYNE, Robert, F.
发明人： PAYNE, Robert, F.
IPC分类号： G11C7/06
CPC分类号： H03K3/2885
摘要： Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the invention provide comparator circuits with a preamplifier circuit, a latch circuit (200) and a current steering circuit. The current steering circuit applies a current to the preamplifier circuit during a transparent phase, and applies the same current to the latch circuit during a latch phase.
摘要翻译：本文公开了用于比较信号的各种系统和方法。例如，本发明的一些实施例为比较器电路提供前置放大器电路，锁存电路（200）和电流转向电路。电流转向电路在透明相位期间向前置放大器电路施加电流，并且在锁存阶段期间将相同的电流施加到锁存电路。

2. 发明申请

WO2013152196A1 INTERCHIP COMMUNICATION USING AN EMBEDDDED DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：使用嵌入式电介质波导的交互通信
公开(公告)号：WO2013152196A1
公开(公告)日：2013-10-10
申请号：PCT/US2013/035281
申请日：2013-04-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LI ITED
发明人： HERBSOMMER, Juan, A. , PAYNE, Robert, F. , CORSI, Marco , HAROUN, Baher, S. , ALI, Hassan
IPC分类号： G02B6/06 , G02B6/02
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/16 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly (206-A1) with a package substrate (304-A) and an integrated circuit (IC) (302-A). The package substrate has a microstrip line (208-A1), and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board (202-A) is also secured to the package substrate. A dielectric waveguide (204- A) is secured to the circuit board. The dielectric waveguide has a dielectric core (310-A) that extends into a transition region (314- A) located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装衬底（304-A）和集成电路（IC）（302-A）的电路组件（206-A1）。封装衬底具有微带线（208-A1），并且IC被固定到封装衬底并且电耦合到微带线。电路板（202-A）也固定到封装衬底。电介质波导（204-A）固定到电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域（314-A）中的介质芯（310-A），并且微带线被配置为与介质波导形成通信链路。

3. 发明申请

WO2012024371A3 TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH 审中-公开
公开(公告)号：WO2012024371A3
公开(公告)日：2012-02-23
申请号：PCT/US2011/048037
申请日：2011-08-17
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , PAYNE, Robert, F. , CORSI, Marco
发明人： PAYNE, Robert, F. , CORSI, Marco
IPC分类号： H03M1/12 , H03M1/66
摘要： An analog-to-digital converter (ADC) 400 converts analog input signal X(t) to a digital signal Y[n]. To do this, divider 402 divides a clock signal CLK (with a frequency of F s or period of T s ) into M clock signals (each with a frequency of F s /M) that are staggered by delay circuits 418- 1 to 418-M and provided to ADCs 410- 1 to 410-M. This allows each of ADCs 410- 1 to 410-M to convert the analog signal X(t) to digital signals X 1 (k) to X(k). The gain and DC offset adjustments are applied to digital signals X 1 (k) to Χ Μ (k) by correction circuits 416- 1 to 416-M to generate digital signals Y[1] to Y[M], which can then be multiplexed by multiplexer 408 to generate the digital signal Y[N].

4. 发明申请

WO2009012373A1 HIGH SPEED LATCHED COMPARATOR 审中-公开
标题翻译：高速封锁比较器
公开(公告)号：WO2009012373A1
公开(公告)日：2009-01-22
申请号：PCT/US2008/070310
申请日：2008-07-17
申请人： TEXAS INSTRUMENTS INCORPORATED , PAYNE, Robert, F. , CORSI, Marco
发明人： PAYNE, Robert, F. , CORSI, Marco
IPC分类号： H03K5/08
CPC分类号： H03K3/356139
摘要： An improved latched comparator (100), including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors (103, 104) having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor. The latch and track select circuit includes a further transistor having an source connected to a current sink (105, 106) connected to ground, having a gate connected to receive a track signal and having a drain connected to the common connection node of the first and second transistors, and a still further transistor having a source connected to the current sink connected to ground, having a gate connected to receive a latch signal and having a drain connected to the common connection node of the third and fourth transistors. Bipolar embodiments are also included.
摘要翻译：一种改进的锁存比较器（100），包括轨道模式电路，锁存器和锁存和轨道选择电路。轨道模式电路包括其源极连接在一起的两个晶体管（103,104），并且它们各自的栅极接收相应的第一和第二输入端，并且它们的漏极由相应的电阻器连接到电源。锁存器包括另外两个晶体管，其源极连接在一起，每个晶体管连接到另一个的漏极，并且其漏极连接到第一晶体管和第一电阻器的公共连接节点中的相应一个，晶体管和第二个电阻。锁存和轨道选择电路包括另外的晶体管，其具有连接到连接到地的电流宿（105,106）的源极，其具有连接到栅极的栅极，其接收轨道信号并且具有连接到第一和第二公共连接节点的漏极，第二晶体管和另一晶体管，其源极连接到连接到地的电流宿，具有连接到接收锁存信号的栅极，并且具有连接到第三和第四晶体管的公共连接节点的漏极。还包括双极实施例。

5. 发明申请

WO2008079663A1 PARALLEL BIPOLAR LOGIC DEVICES AND METHODS FOR USING SUCH 审中-公开
标题翻译：并行双极性逻辑器件及其使用方法
公开(公告)号：WO2008079663A1
公开(公告)日：2008-07-03
申请号：PCT/US2007/087086
申请日：2007-12-11
申请人： TEXAS INSTRUMENTS INCORPORATED , PAYNE, Robert, F.
发明人： PAYNE, Robert, F.
IPC分类号： H03K19/082
CPC分类号： H03K19/20
摘要： Various logic gates and methods for using such are disclosed herein. For example, some embodiments of the invention provide parallel differential logic gates (300). Such logic gates include two or more differential input pairs (307, 311). The collectors of the first transistors (306, 310) in each of the differential pairs are all electrically coupled to an upper voltage (330) via a first load resistor (302). Similarly, the collectors of the second transistors (308, 312) in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor (304). Depending upon the relative values selected for the first and second load resistors, the gate operates as an AND gate or an OR gate.
摘要翻译：本文公开了各种逻辑门及其使用方法。例如，本发明的一些实施例提供并行差分逻辑门（300）。这种逻辑门包括两个或更多个差分输入对（307,311）。每个差分对中的第一晶体管（306,310）的集电极都经由第一负载电阻（302）电耦合到上电压（330）。类似地，每个差分对中的第二晶体管（308,312）的集电极都经由第二负载电阻（304）电耦合到上电压。根据为第一和第二负载电阻选择的相对值，门作为“与”门或“或”门。

6. 发明申请

WO2013152191A1 INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：使用介质波导的交互通信
公开(公告)号：WO2013152191A1
公开(公告)日：2013-10-10
申请号：PCT/US2013/035273
申请日：2013-04-04
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： HERBSOMMER, Juan, A. , PAYNE, Robert, F. , CORSI, Marco , HAROUN, Baher, S. , ALI, Hassan
IPC分类号： G02B6/10 , G02B6/02
CPC分类号： H05K1/0239 , G02B6/12004 , G02B6/1228 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/16 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K1/115 , H05K1/18 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly (206-A1) with a package substrate (304-A) and an integrated circuit (IC) (302-A). The package substrate has a microstrip line (208-A1), and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board (202-A) is also secured to the package substrate. A dielectric waveguide (204- A) is secured to the circuit board. The dielectric waveguide has a dielectric core (310-A) that extends into a transition region (314- A) located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装衬底（304-A）和集成电路（IC）（302-A）的电路组件（206-A1）。封装衬底具有微带线（208-A1），并且IC被固定到封装衬底并且电耦合到微带线。电路板（202-A）也固定到封装衬底。电介质波导（204-A）固定到电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域（314-A）中的介质芯（310-A），并且微带线被配置为与介质波导形成通信链路。

7. 发明申请

WO2012037133A1 MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING 审中-公开
标题翻译：多功能放大器，具有降低玻璃化
公开(公告)号：WO2012037133A1
公开(公告)日：2012-03-22
申请号：PCT/US2011/051411
申请日：2011-09-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , PAYNE, Robert, F.
发明人： PAYNE, Robert, F.
IPC分类号： H03F3/45 , H03K17/62 , H03M1/12
CPC分类号： H03M1/0872 , H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： A first multiplexer (216-1) is coupled to a first input terminal (IΝΡ1/ΙΝΡ2) and a second multiplexer (216-2) is coupled to a second input terminal (IΝΜ1/ΙΝΜ2) of a folded cascode differential amplifier (210) which includes transistors (Q1 through Q4) and current sources (222-228). Switching between differential input signals (INP1/INM1) and (INP2/INM2) is controlled through a select signal SELECT provided by a controller (214). A reset mechanism includes a switch (Q5) coupled between output terminals (OUTP, OUTM) of amplifier (210) and controlled by a pulse generator (XOR gate 218 and delay circuit 220). On a rising or falling edge of the select signal SELECT, a pulse is provided to activate the switch (Q5) so as to briefly short the output terminals (OUTP, OUTM). This avoids glitching and results in faster settling times.
摘要翻译：第一多路复用器（216-1）耦合到第一输入端（I→1/2），第二多路复用器（216-2）耦合到第二输入端（I 1/1 / 包括晶体管（Q1至Q4）和电流源（222-228）的折叠共源共栅差分放大器（210）的电流（λ2）。通过由控制器（214）提供的选择信号SELECT来控制差分输入信号（INP1 / INM1）和（INP2 / INM2）之间的切换。复位机构包括耦合在放大器（210）的输出端（OUTP，OUTM）之间并由脉冲发生器（XOR门218和延迟电路220）控制的开关（Q5）。在选择信号SELECT的上升沿或下降沿，提供脉冲以激活开关（Q5），以短暂地输出端子（OUTP，OUTM）。这避免了毛刺，并导致更快的沉降时间。

8. 发明申请

WO2014134343A1 DIELECTRIC WAVEGUIDE METHODS AND APPARATUS 审中-公开
标题翻译：电介质波导方法和装置
公开(公告)号：WO2014134343A1
公开(公告)日：2014-09-04
申请号：PCT/US2014/019108
申请日：2014-02-27
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS DEUTSCHLAND GMBH , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HERBSOMMER, Juan, A. , SCHUPPENER, Gerd , PAYNE, Robert, F.
IPC分类号： H01P3/00
CPC分类号： H01P3/16 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01P1/04 , H01P3/121 , H01Q13/00 , H05K1/0239 , H05K1/024 , H05K2201/0187 , H05K2201/0195 , H05K2201/09618 , H05K2201/10098 , Y10T29/49826 , Y10T29/49908
摘要： A dielectric waveguide (DWG) (1020) has a dielectric core member that has a first dielectric constant value. A cladding surrounding the dielectric core member has a second dielectric constant value that is lower than the first dielectric constant. A mating end of the waveguide is configured in a non-planer shape for mating with a second waveguide having a matching non-planar shaped mating end. In an example, DWG (1020) has an interface surface on its side at each end for interfacing with antennas on the back side of chip scale package (CSP) (1040-1) and (1040-2) which allows DWG (1020) to be mounted horizontally from chip to chip. In an embodiment, a deformable material is disposed on the surface of the mating end of the waveguide, such that when mated to a second waveguide, the deformable material fills a gap region between the mating ends of the waveguide and the second waveguide.
摘要翻译：电介质波导（DWG）（1020）具有具有第一介电常数值的介质芯构件。围绕介电芯构件的包层具有低于第一介电常数的第二介电常数值。波导的配合端构造成非平面形状，用于与具有匹配的非平面形状配合端的第二波导配合。在一个示例中，DWG（1020）在其每端具有在其侧面上的接口表面，用于与芯片级封装（CSP）（1040-1）和（1040-2）的背侧上的天线接口，其允许DWG（1020）从芯片到芯片水平安装。在一个实施例中，可变形材料设置在波导的配合端的表面上，使得当与第二波导配合时，可变形材料填充波导的配合端和第二波导之间的间隙区域。

9. 发明申请

WO2013152226A1 INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES 审中-公开
标题翻译：使用嵌入式电介质和金属波导的交互通信
公开(公告)号：WO2013152226A1
公开(公告)日：2013-10-10
申请号：PCT/US2013/035322
申请日：2013-04-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HERBSOMMER, Juan, A. , PAYNE, Robert, F. , CORSI, Marco , HAROUN, Baher, S. , ALI, Hassan
IPC分类号： G02B6/12 , G02B6/10
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/122 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly (206-A1) with a package substrate (304-A) and an integrated circuit (IC) (302-A). The package substrate has a microstrip line (208-A1), and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board (202-A) is also secured to the package substrate. A dielectric waveguide (204- A) is secured to the circuit board. The dielectric waveguide has a dielectric core (310-A) that extends into a transition region (314- A) located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装衬底（304-A）和集成电路（IC）（302-A）的电路组件（206-A1）。封装衬底具有微带线（208-A1），并且IC被固定到封装衬底并且电耦合到微带线。电路板（202-A）也固定到封装衬底。电介质波导（204-A）固定到电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域（314-A）中的介质芯（310-A），并且微带线被配置为与介质波导形成通信链路。

10. 发明申请

WO2013059771A1 METHOD AND APPARATUS FOR PERFORMING SPECULATIVE DECISION FEEDBACK EQUALIZATION 审中-公开
标题翻译：用于执行分布式决策反馈均衡的方法和装置
公开(公告)号：WO2013059771A1
公开(公告)日：2013-04-25
申请号：PCT/US2012/061272
申请日：2012-10-22
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , WARKE, Nirmal, C. , PAYNE, Robert, F.
发明人： WARKE, Nirmal, C. , PAYNE, Robert, F.
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/03343 , H04L25/14 , H04L27/01 , H04L2025/0349
摘要： A method and apparatus for equalizing a received signal are provided. The signal is filtered and transmitted over a channel (104) using an encoding scheme having transmit symbols. An example SerDes link 300 employs an non-return zero (NRZ) encoding scheme. The transmitted signal is shaped such that a transmit filter (302) (e.g., a FIR filter) and an equalizer (304) adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative digital front end (DFE) circuit (305) with significantly reduced comparator levels.
摘要翻译：提供了一种用于均衡接收信号的方法和装置。信号被滤波并通过信道（104）使用具有发送符号的编码方案进行发送。 SerDes链路300的示例采用非归零（NRZ）编码方案。传输的信号被成形为使得发射滤波器（302）（例如，FIR滤波器）和均衡器（304）调整均衡窗口中的一组抽头，使得来自该组的抽头基本上彼此相等。然后使用具有显着降低的比较器电平的推测数字前端（DFE）电路（305）在均衡信号中补偿符号间干扰。

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