专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007038480A1 PIN ELECTRONICS DRIVER 审中-公开
标题翻译： PIN电子驱动器
公开(公告)号：WO2007038480A1
公开(公告)日：2007-04-05
申请号：PCT/US2006/037413
申请日：2006-09-26
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A.
发明人： SARTSCHEV, Ronald, A.
IPC分类号： G01R31/319
CPC分类号： G01R31/31924
摘要： Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.
摘要翻译：用于驱动装置的引脚的电路包括终止于第一阻抗的第一电路路径，终止于第二阻抗的第二电路路径，其中第二阻抗小于第一阻抗，以及选择电路，用于控制第二阻抗的操作电路路径。当第二电路不配置用于操作时，第一电路路径被配置为输出多个第一电压信号中的一个。当第二电路路径被配置用于操作时，第二电路路径被配置为输出第二电压信号。第二电压信号大于多个第一电压信号。

2. 发明申请

WO2007038340A2 STROBE TECHNIQUE FOR TIME STAMPING A DIGITAL SIGNAL 审中-公开
标题翻译：时间标记数字信号的频闪技术
公开(公告)号：WO2007038340A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/037100
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.
摘要翻译：系统和设备生成时间戳以识别和记录诸如在数据信号或时钟信号中接收的边缘的事件的时间。一组选通脉冲可以通过将外部时钟信号路由到延迟增加的延迟值的延迟元件来产生。数据信号或被测设备时钟信号可以被施加到由选通脉冲计时的一组锁存器中的每一个的输入。该组锁存器由此可以捕获数据信号或时钟信号的一系列样本。一系列采样可以被编码为一个时钟周期内的边沿时间。时钟周期计数器可以添加到边缘时间以生成时间戳。

3. 发明申请

WO2008144486A1 CALIBRATING JITTER 审中-公开
标题翻译：校准抖动
公开(公告)号：WO2008144486A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/063865
申请日：2008-05-16
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P. , HUANG, Li
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P. , HUANG, Li
IPC分类号： H04B17/00
CPC分类号： H04L1/205 , G01R31/31709 , H04B17/21
摘要： Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.
摘要翻译：在测试设备与待测设备（DUT）的连接之间的通信通道中的校准抖动包括在连接点附近的通信信道中的采样测试数据，以产生采样数据，其中测试数据通过通信信道第一速率，并且其中测试数据以小于第一速率的第二速率进行采样，确定相对于测试数据的采样数据中的第一抖动量，以及在该点处确定第二抖动量基于第一个抖动量的连接。

4. 发明申请

WO2006068966A1 USING A PARAMETRIC MEASUREMENT UNIT TO SENSE A VOLTAGE AT A DEVICE UNDER TEST 审中-公开
标题翻译：使用参数测量单元在测试下的设备上感测电压
公开(公告)号：WO2006068966A1
公开(公告)日：2006-06-29
申请号：PCT/US2005/045705
申请日：2005-12-16
申请人： TERADYNE, INC. , WALKER, Ernest, P. , SARTSCHEV, Ronald, A.
发明人： WALKER, Ernest, P. , SARTSCHEV, Ronald, A.
IPC分类号： G01R31/28
CPC分类号： G01R31/31924
摘要： Circuitry for use in testing a device includes a first measurement unit to apply a forced voltage to the device, and a second measurement unit having functionality that is disabled. The second measurement unit includes a sense path to receive a sensed voltage from the device, where the sense path connects to the first measurement unit through the second measurement unit. The first measurement unit adjusts the forced voltage based on the sensed voltage.
摘要翻译：用于测试设备的电路包括用于向该设备施加强制电压的第一测量单元和具有禁用功能的第二测量单元。第二测量单元包括用于从设备接收感测电压的感测路径，其中感测路径通过第二测量单元连接到第一测量单元。第一测量单元基于感测的电压来调节强制电压。

5. 发明申请

WO2007038339A2 STROBE TECHNIQUE FOR RECOVERING A CLOCK IN A DIGITAL SIGNAL 审中-公开
标题翻译：用于在数字信号中恢复时钟的STROBE技术
公开(公告)号：WO2007038339A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/037099
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.
摘要翻译：提供了一种方法和装置，用于恢复嵌入诸如数据信号的数字信号中的时钟信息。可以通过将边沿发生器路由到具有递增增加的延迟值的延迟元件来产生一组选通脉冲。通过来自边沿发生器的递增延迟信号触发的一组锁存器可以捕获数据信号的采样。编码器可以将样本转换为表示采样信号的边沿时间和极性的字。表示边缘时间的字可以存储在存储器中。累加器可以收集N个样本的平均边缘时间。平均边沿时间可以用固定的去偏移值进行调整，形成提取的时钟信息。提取的时钟信息可以用作指向存储在存储器中的字的指针。

6. 发明申请

WO2007038233A2 STROBE TECHNIQUE FOR TEST OF DIGITAL SIGNAL TIMING 审中-公开
标题翻译：用于数字信号时序测试的STROBE技术
公开(公告)号：WO2007038233A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/036912
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
摘要翻译：测试系统定时方法模拟被测设备上同步时钟的时序。可以通过将边沿发生器路由到具有逐渐增加的延迟值的延迟元件来产生选通脉冲。可以将数据信号或同步时钟信号施加到由选通脉冲计时的一组锁存器中的每一个的输入。编码器可以将由此锁存的一系列样本转换成表示采样信号的边沿时间和极性的字。如果采样信号是数据信号，则该字可以存储在存储器中。如果采样信号是时钟信号，则该字路由到时钟总线，用于寻址存储器。提供时钟边沿时间和数据边沿时间之间的差异，并将其与预期值进行比较。

7. 发明申请

WO2015069465A1 AUTOMATED TEST SYSTEM WITH EVENT DETECTION CAPABILITY 审中-公开
标题翻译：具有事件检测能力的自动测试系统
公开(公告)号：WO2015069465A1
公开(公告)日：2015-05-14
申请号：PCT/US2014/061933
申请日：2014-10-23
申请人： TERADYNE, INC.
发明人： SARTSCHEV, Ronald, A. , SENG, Edward, J. , HUTNER, Marc, Reuben
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01R31/31922 , G01R31/31703 , G01R31/31722 , G01R31/31727 , G01R31/318594 , G01R31/31917 , G01R31/31928 , G01R31/31932 , H04L1/242 , H04L27/0008 , H04L27/2053 , H04L27/22 , H04L27/38
摘要： A test technique that may be implemented in an automated test system for testing semiconductor devices. The test technique may enable the fast detection of a signal transition, such as an edge, within a waveform and the timing of that event. Circuitry within a digital instrument that can be quickly and flexibly programmed may, at least in part, implement the test technique. That circuitry may be simply programmed with testing parameters, such that application of the technique may lead to faster test development and faster times. In operation, that circuitry receives parameters specifying parameters of a window over a waveform in which samples of the waveform will be taken to detect the signal transition. The circuitry may convert these parameters into control signals for other components in the test system, such as an edge generator or pin electronics, to take a programmed number of samples at desired times.
摘要翻译：可以在用于测试半导体器件的自动化测试系统中实现的测试技术。测试技术可以使得能够快速检测波形内的信号转换（例如边沿）以及该事件的定时。可以快速灵活地编程的数字仪器内的电路可以至少部分地实现测试技术。该电路可以简单地用测试参数编程，使得该技术的应用可以导致更快的测试开发和更快的时间。在操作中，该电路接收指定波形的参数的参数，其中将采取波形的采样来检测信号转换。电路可以将这些参数转换成测试系统中的其他部件（例如边缘发生器或引脚电子器件）的控制信号，以在期望的时间采取编程的样本数量。

8. 发明申请

WO2015077277A1 AUTOMATED TEST SYSTEM WITH EDGE STEERING 审中-公开
标题翻译：具有边缘转向的自动测试系统
公开(公告)号：WO2015077277A1
公开(公告)日：2015-05-28
申请号：PCT/US2014/066295
申请日：2014-11-19
申请人： TERADYNE, INC.
发明人： LIN, Howard , CHAMPION, Corbin, L. , VANDER WAGT, Jan Paul, Anthonie , SARTSCHEV, Ronald, A.
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01R31/31922
摘要： A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
摘要翻译：可以通过自动测试系统来测试半导体器件测试（DUT），该测试系统处理指定每个测试器周期的边缘数量的测试程序，其可能大于测试仪能够产生的边缘数量。测试系统可以包括基于在该周期和/或先前周期中指定测试仪的操作的数据减少测试程序的每个周期中的边缘数量的电路。这样的减少通过减少每个通道的定时游标的总数来简化实现边缘发生器所需的电路。尽管如此，保留测试系统编程的灵活性。

9. 发明申请

WO2013148085A1 EDGE TRIGGERED CALIBRATION 审中-公开
标题翻译：边缘触发校准
公开(公告)号：WO2013148085A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/029121
申请日：2013-03-05
申请人： TERADYNE, INC.
发明人： VAN DER WAGT, Jan Paul Anthonie , SARTSCHEV, Ronald, A. , KANNALL, Gregory, A.
IPC分类号： G01R23/02 , G01R29/02
CPC分类号： H01L22/34 , G01R31/3191 , G01R31/31922 , H01L2924/0002 , H01L2924/00
摘要： Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one- shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system.
摘要翻译：用于测量电路路径中的传播延迟的电路。该电路包括一个单触发边沿触发元件，可以与回路连接在一个回路中。通过电路路径传播的边沿信号触发单触发元件输出脉冲。脉冲在环路周围传播，再次触发单触发元件产生脉冲，产生重复的一系列脉冲。这些脉冲之间的周期受到通过环路的边缘的传播时间的影响，使得与环路中连接并未连接的电路路径的周期的差异指示电路路径中的传播延迟。这样的电路可以被配置为独立地测量并因此校准与上升沿和下降沿相关联的传播延迟。校准以分别均衡上升沿和下降沿的传播延迟可以增加自动测试系统的定时精度。

10. 发明申请

WO2003054565A1 COMPACT ATE WITH TIMESTAMP SYSTEM 审中-公开
标题翻译：紧凑型与TIMESTAMP系统
公开(公告)号：WO2003054565A1
公开(公告)日：2003-07-03
申请号：PCT/US2002/039658
申请日：2002-12-11
申请人： TERADYNE, INC.
发明人： SARTSCHEV, Ronald, A. , XU, Jun
IPC分类号： G01R31/3193
CPC分类号： G11C29/56012 , G01R31/3193 , G01R31/31937 , G11C29/56
摘要： A accurate time measurement circuit (100). The design is amenable to implementation as a CMOS integrated circuits, making the circuit suitable for a highly integrated system, such as automatic test equipment where multiple time measurement circuits are required. The circuit uses a delay locked loop (210) to generate a plurality of signals that are delayed in time by an interval D. The signal is fed to a bank of delay elements, (230) each with a slightly different delay with the difference in delay between the first and the last being more than D. An accurate time measurement is achieved by finding coincidence between one of the TAP signals and one of the delay signals. The circuit has much greater accuracy than a traditional delay line based time measurement circuit with the same number of taps. It therefore provides both accuracy and fast re-fire time and is less susceptible to noise.
摘要翻译：精确的时间测量电路（100）。该设计适合作为CMOS集成电路的实现，使得该电路适合于高度集成的系统，例如需要多个时间测量电路的自动测试设备。电路使用延迟锁定环（210）来产生在时间上延迟了间隔D的多个信号。该信号被馈送到一组延迟元件（230），每个延迟元件具有略微不同的延迟，第一个和最后一个之间的延迟大于D.通过发现一个TAP信号和一个延迟信号之间的一致，实现精确的时间测量。该电路具有比具有相同数量的抽头的传统的基于延迟线的时间测量电路具有更大的精度。因此，它提供准确性和快速重燃时间，并且不易受噪音影响。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式