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1. 发明申请

WO2008144486A1 CALIBRATING JITTER 审中-公开
标题翻译：校准抖动
公开(公告)号：WO2008144486A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/063865
申请日：2008-05-16
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P. , HUANG, Li
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P. , HUANG, Li
IPC分类号： H04B17/00
CPC分类号： H04L1/205 , G01R31/31709 , H04B17/21
摘要： Calibrating jitter in a communication channel between test equipment and a connection for a device under test (DUT) includes sampling test data in the communication channel at about a point of the connection to produce sampled data, where the test data travels through the communication channel at a first rate, and where the test data is sampled at a second rate that is less than the first rate, determining a first amount of jitter in the sampled data relative to the test data, and determining a second amount of jitter at about the point of connection based on the first amount of jitter.
摘要翻译：在测试设备与待测设备（DUT）的连接之间的通信通道中的校准抖动包括在连接点附近的通信信道中的采样测试数据，以产生采样数据，其中测试数据通过通信信道第一速率，并且其中测试数据以小于第一速率的第二速率进行采样，确定相对于测试数据的采样数据中的第一抖动量，以及在该点处确定第二抖动量基于第一个抖动量的连接。

2. 发明申请

WO2007038340A2 STROBE TECHNIQUE FOR TIME STAMPING A DIGITAL SIGNAL 审中-公开
标题翻译：时间标记数字信号的频闪技术
公开(公告)号：WO2007038340A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/037100
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.
摘要翻译：系统和设备生成时间戳以识别和记录诸如在数据信号或时钟信号中接收的边缘的事件的时间。一组选通脉冲可以通过将外部时钟信号路由到延迟增加的延迟值的延迟元件来产生。数据信号或被测设备时钟信号可以被施加到由选通脉冲计时的一组锁存器中的每一个的输入。该组锁存器由此可以捕获数据信号或时钟信号的一系列样本。一系列采样可以被编码为一个时钟周期内的边沿时间。时钟周期计数器可以添加到边缘时间以生成时间戳。

3. 发明申请

WO2006068966A1 USING A PARAMETRIC MEASUREMENT UNIT TO SENSE A VOLTAGE AT A DEVICE UNDER TEST 审中-公开
标题翻译：使用参数测量单元在测试下的设备上感测电压
公开(公告)号：WO2006068966A1
公开(公告)日：2006-06-29
申请号：PCT/US2005/045705
申请日：2005-12-16
申请人： TERADYNE, INC. , WALKER, Ernest, P. , SARTSCHEV, Ronald, A.
发明人： WALKER, Ernest, P. , SARTSCHEV, Ronald, A.
IPC分类号： G01R31/28
CPC分类号： G01R31/31924
摘要： Circuitry for use in testing a device includes a first measurement unit to apply a forced voltage to the device, and a second measurement unit having functionality that is disabled. The second measurement unit includes a sense path to receive a sensed voltage from the device, where the sense path connects to the first measurement unit through the second measurement unit. The first measurement unit adjusts the forced voltage based on the sensed voltage.
摘要翻译：用于测试设备的电路包括用于向该设备施加强制电压的第一测量单元和具有禁用功能的第二测量单元。第二测量单元包括用于从设备接收感测电压的感测路径，其中感测路径通过第二测量单元连接到第一测量单元。第一测量单元基于感测的电压来调节强制电压。

4. 发明申请

WO2007038339A2 STROBE TECHNIQUE FOR RECOVERING A CLOCK IN A DIGITAL SIGNAL 审中-公开
标题翻译：用于在数字信号中恢复时钟的STROBE技术
公开(公告)号：WO2007038339A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/037099
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.
摘要翻译：提供了一种方法和装置，用于恢复嵌入诸如数据信号的数字信号中的时钟信息。可以通过将边沿发生器路由到具有递增增加的延迟值的延迟元件来产生一组选通脉冲。通过来自边沿发生器的递增延迟信号触发的一组锁存器可以捕获数据信号的采样。编码器可以将样本转换为表示采样信号的边沿时间和极性的字。表示边缘时间的字可以存储在存储器中。累加器可以收集N个样本的平均边缘时间。平均边沿时间可以用固定的去偏移值进行调整，形成提取的时钟信息。提取的时钟信息可以用作指向存储在存储器中的字的指针。

5. 发明申请

WO2007038233A2 STROBE TECHNIQUE FOR TEST OF DIGITAL SIGNAL TIMING 审中-公开
标题翻译：用于数字信号时序测试的STROBE技术
公开(公告)号：WO2007038233A2
公开(公告)日：2007-04-05
申请号：PCT/US2006/036912
申请日：2006-09-22
申请人： TERADYNE, INC. , SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
发明人： SARTSCHEV, Ronald, A. , WALKER, Ernest, P.
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
摘要翻译：测试系统定时方法模拟被测设备上同步时钟的时序。可以通过将边沿发生器路由到具有逐渐增加的延迟值的延迟元件来产生选通脉冲。可以将数据信号或同步时钟信号施加到由选通脉冲计时的一组锁存器中的每一个的输入。编码器可以将由此锁存的一系列样本转换成表示采样信号的边沿时间和极性的字。如果采样信号是数据信号，则该字可以存储在存储器中。如果采样信号是时钟信号，则该字路由到时钟总线，用于寻址存储器。提供时钟边沿时间和数据边沿时间之间的差异，并将其与预期值进行比较。

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