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1. 发明申请

WO2003009134A1 VALUE PREDICTION IN A PROCESSOR FOR PROVIDING SPECULATIVE EXECUTION 审中-公开
标题翻译：用于提供分析性执行的处理者的价值预测
公开(公告)号：WO2003009134A1
公开(公告)日：2003-01-30
申请号：PCT/SE2002/000298
申请日：2002-02-21
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , WINBERG, Lars , HOLMBERG, Per
发明人： WINBERG, Lars , HOLMBERG, Per
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/383 , G06F9/3832 , G06F9/3838 , G06F9/3842
摘要： The present invention relates to a processing unit (1) for executing instructions in a computer system and to a method in such a processing unit. According to the present invention a decision is made whether or not to base execution on a value prediction (P), wherein the decision is based on information associated with the estimated time gain of execution based on a correct prediction. According to an embodiment of the present invention the decision regarding whether or not to execute speculatively is based on information (14) regarding whether a cache hit or a cache miss is detected in connection with a load instruction. In an alternative embodiment of the present invention the decision is based on information regarding the dependency depth of the load instruction, i.e. the number of instructions that are dependent on the load.
摘要翻译：本发明涉及一种用于在计算机系统中执行指令的处理单元（1）以及这种处理单元中的方法。根据本发明，判定是否将执行值基于值预测（P），其中，所述判定基于与基于正确预测的估计的执行时间增益相关联的信息。根据本发明的实施例，关于是否以推测方式执行的决定是基于关于是否与加载指令相关联地检测到高速缓存命中或高速缓存未命中的信息（14）。在本发明的替代实施例中，该决定基于关于加载指令的依赖深度的信息，即依赖于负载的指令的数量。

2. 发明申请

WO2006110069A1 DATA VALUE COHERENCE IN COMPUTER SYSTEMS 审中-公开
标题翻译：计算机系统中的数据值相关性
公开(公告)号：WO2006110069A1
公开(公告)日：2006-10-19
申请号：PCT/SE2005/000534
申请日：2005-04-13
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ) , WINBERG, Mats , WINBERG, Lars , LINNERMARK, Nils, Ola , HEMETEK, Marijan
发明人： WINBERG, Mats , WINBERG, Lars , LINNERMARK, Nils, Ola , HEMETEK, Marijan
IPC分类号： G06F9/45 , G06F11/36
CPC分类号： G06F11/3628 , G06F8/41 , G06F11/3624
摘要： The invention concerns the general data value problem, and especially the residence problem in a computer system when executing program code translated from a source code representation (10) into a target code representation (30). A basic idea of the invention is to associate references to target data value containers (40) in the target code with corresponding address information of original data value containers (20) of the source code during program code translation, and store information related to target code instructions together with associated address information of original data value containers at execution of target code to uphold a data value view (50) of the original source code representation. In this way, tracking of data values of original source code (10) at execution of translated target code (30) in a target system is supported in a highly efficient manner.
摘要翻译：本发明涉及一般的数据价值问题，特别是当执行从源代码表示（10）转换为目标代码表示（30）的程序代码时计算机系统中的居住问题。本发明的基本思想是在程序代码转换中将目标代码中的目标数据值容器（40）与源代码的原始数据值容器（20）的相应地址信息相关联，并存储与目标代码相关的信息指令以及执行目标代码的原始数据值容器的关联地址信息，以维护原始源代码表示的数据值视图（50）。以这种方式，以高效的方式支持在目标系统中执行转换的目标代码（30）时原始源代码（10）的数据值的跟踪。

3. 发明申请

WO2003091972A1 MEMORY ACCESS REGISTER FILE 审中-公开
标题翻译：存储器访问寄存器文件
公开(公告)号：WO2003091972A1
公开(公告)日：2003-11-06
申请号：PCT/SE2002/000835
申请日：2002-04-26
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , HOLMBERG, Per, Anders , WINBERG, Lars , STRÖMBERGSON, Karl, Oscar, Joachim
发明人： HOLMBERG, Per, Anders , WINBERG, Lars , STRÖMBERGSON, Karl, Oscar, Joachim
IPC分类号： G09F9/30
CPC分类号： G06F9/30101 , G06F9/30043 , G06F9/3885
摘要： The general idea according to the invention is to introduce a special-purpose register file (34) adapted for holding memory address calculation information received from memory (50, 70) and to provide one or more dedicated interfaces (73, 74) for allowing efficient transfer of memory address calculation information in relation to the special-purpose register file. The special-purpose register file (34) is preferably connected to at least one functional processor unit (42), which is operable for determining a memory address based on memory address calculation information received from the special-purpose register file (34). Once the memory address has been determined, the corresponding memory access can be effectuated.
摘要翻译：根据本发明的一般想法是引入一个专用寄存器文件（34），适用于保存从存储器（50,70）接收的存储器地址计算信息并提供一个或多个专用接口（73,74），用于允许有效的传送与专用寄存器文件相关的存储器地址计算信息。专用寄存器文件（34）优选地连接到至少一个功能处理器单元（42），其可操作用于基于从专用寄存器文件（34）接收的存储器地址计算信息来确定存储器地址。一旦确定了存储器地址，就可以实现相应的存储器访问。

4. 发明申请

WO2003032154A1 HIDDEN JOB START PREPARATION IN AN INSTRUCTION-PARALLEL PROCESSOR SYSTEM 审中-公开
标题翻译：指令并行处理器系统中的隐藏作业开始准备
公开(公告)号：WO2003032154A1
公开(公告)日：2003-04-17
申请号：PCT/SE2001/002183
申请日：2001-10-08
申请人： TELEFONAKTIEBOLAGET LM ERICSSON , ERICSSON, Tomas , HOLMBERG, Per, Anders , STRANDBERG, Fredrik , WINBERG, Lars , LINNERMARK, Nils, Ola
发明人： ERICSSON, Tomas , HOLMBERG, Per, Anders , STRANDBERG, Fredrik , WINBERG, Lars , LINNERMARK, Nils, Ola
IPC分类号： G06F9/38
CPC分类号： G06F9/4843
摘要： The read latency caused by job start preparation of a future job is at least partly hidden within the current job by reading information for job start preparation of the future job integrated with the execution of the current job. Instructions for job start preparation are preferably instrumented (701) into the current job and executed (702), whenever possible, in parallel with the instructions of the current job. The integrated job start preparation may include table look-ups, register file updating, instruction fetching and preparation. If the scheduled job order is allowed to change during execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution of the next job and take appropriate actions (704; 705, 706) dpending on the outcome of the test. In addition to reduced job start preparation time, unused slots in the instruction-parallel execution of the current job may be filled up by the added read instructions, thus providing more efficient utilization of the multiple functional execution units of the processor.
摘要翻译：由作业开始准备未来作业引起的读延迟至少部分隐藏在当前作业中，通过阅读与当前作业的执行相集成的未来作业的作业开始准备的信息。最好将作业开始准备的说明书（701）装入当前作业，并尽可能与当前作业的指令并行执行（702）。集成作业开始准备可以包括表查找，寄存器文件更新，指令提取和准备。如果在执行期间允许调度的作业命令改变，则在开始执行之前通常需要测试（703）下一个作业是否仍然有效，通常需要测试（703）下一个作业是否仍然有效开始执行下一个工作，并对测试结果采取适当的措施（704; 705,706）。除了减少作业开始准备时间之外，当前作业的指令并行执行中的未使用的插槽可以被添加的读取指令填充，从而提供对处理器的多个功能执行单元的更有效的利用。

5. 发明申请

WO2017039508A1 SYSTEM, METHOD, AND APPARATUS FOR OPTICAL BROADCAST TRANSMISSION IN A CIRCUIT BOARD 审中-公开
标题翻译：电路板中广播广播传输的系统，方法和装置
公开(公告)号：WO2017039508A1
公开(公告)日：2017-03-09
申请号：PCT/SE2015/050931
申请日：2015-09-03
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： REHNSTRÖM, Mats , WINBERG, Lars , PRESS, Marie
IPC分类号： G02B6/42 , G02B6/43
CPC分类号： G02B6/4214 , G02B6/4226 , G02B6/43 , H05K1/0274 , H05K2201/0108 , H05K2201/10121
摘要： A multilayer PCB (160) for optical transmission is presented. The multilayer PCB includes a first layer (1510), a second layer (1520), and a transparent layer (212) between them. The transparent layer may have a first compartment (1851), which may have a first mirror (214) operable to reflect a beam of light (260B) into the first compartment of the transparent layer in a plurality of directions (260C) perpendicular to the direction of the beam of light, thereby transmitting throughout the first compartment an optical signal carried by the beam of light in said plurality of directions such that one or more other mirrors disposed in the first compartment of the transparent layer are able to receive a beam of reflected light (260C) carrying the optical signal. The multilayer PCB may further include a second mirror (1508) in the first compartment for reflecting a wave of reflected light (260C) carrying the optical signal toward an optical receiver (1705).
摘要翻译：提出了一种用于光传输的多层PCB（160）。多层PCB包括第一层（1510），第二层（1520）和它们之间的透明层（212）。透明层可以具有第一隔室（1851），其可以具有第一反射镜（214），该第一反射镜可操作以在垂直于所述透明层的多个方向（260C）将光束（260B）反射到透明层的第一隔室中光束的方向，由此在整个第一隔间内传送由所述多个方向上的光束承载的光信号，使得设置在透明层的第一隔室中的一个或多个其它反射镜能够接收一束承载光信号的反射光（260C）。多层PCB还可以包括第一隔室中的第二反射镜（1508），用于将承载光信号的反射光波（260C）反射向光接收器（1705）。

6. 发明申请

WO2017039507A1 SYSTEM, METHOD, AND APPARATUS FOR PERFORMING ALIGNMENT BETWEEN AN OPTICAL TRANSCEIVER AND AN OPTICAL REFLECTOR 审中-公开
标题翻译：用于执行光收发器和光反射器之间的对准的系统，方法和装置
公开(公告)号：WO2017039507A1
公开(公告)日：2017-03-09
申请号：PCT/SE2015/050930
申请日：2015-09-03
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： REHNSTRÖM, Mats , PRESS, Marie , WINBERG, Lars
IPC分类号： H04B10/11 , G02B6/42 , H01S5/02
CPC分类号： G02B6/4214 , G02B6/4225 , G02B6/4226 , G02B6/43 , H04B10/801
摘要： An apparatus (122) for positioning an optical transceiver (205) relative to a reflector (218) in a multi-layer circuit board (160) is presented. The apparatus includes an optical transceiver (205), a housing (203) in which the optical transceiver (205) is located, a first platform (410), a second platform (420) offset from the first platform (410), and a frame (450) surrounding the second platform (420). The first platform (410) has a first side (413) and a second side (414) opposite the first side (413). The housing (203) is attached to the first side (413). The apparatus further includes a set of actuators comprising a first actuator (442), a second actuator (443), and a third actuator (445), which are connected to the second side (414), and includes a fourth actuator (441) and a fifth actuator (444). Each of the first, second, and third actuators is connected to a first side (421) of the second platform, and is configured such that each can be controlled to move the transceiver (205) by moving along a first axis that is orthogonal to the first side of the second platform, thereby moving the first platform (410). The fourth actuator (441) is attached to the frame and is operable to displace the second platform along a second axis that is orthogonal to the first axis. The fifth actuator (444) is attached to the frame and is operable to displace the second platform along a third axis that is orthogonal to the first axis and to the second axis.
摘要翻译：提出了一种用于在多层电路板（160）中相对于反射器（218）定位光收发器（205）的设备（122）。该装置包括光收发器（205），光收发器（205）所在的壳体（203），第一平台（410），偏离第一平台（410）的第二平台（420）围绕第二平台（420）的框架（450）。第一平台（410）具有与第一侧（413）相对的第一侧（413）和第二侧（414）。壳体（203）附接到第一侧（413）。该装置还包括一组致动器，包括连接到第二侧（414）的第一致动器（442），第二致动器（443）和第三致动器（445），并且包括第四致动器（441）和第五致动器（444）。第一，第二和第三致动器中的每个致动器连接到第二平台的第一侧（421），并且被配置为使得每个致动器可以被控制以通过沿着与第二平台正交的第一轴线移动来移动收发器（205）第二平台的第一侧，从而移动第一平台（410）。第四致动器（441）附接到框架并且可操作以沿着与第一轴线正交的第二轴线移位第二平台。第五致动器（444）附接到框架并且可操作以沿着与第一轴线和第二轴线正交的第三轴线移位第二平台。

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