会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • HIDDEN JOB START PREPARATION IN AN INSTRUCTION-PARALLEL PROCESSOR SYSTEM
    • 指令并行处理器系统中的隐藏作业开始准备
    • WO2003032154A1
    • 2003-04-17
    • PCT/SE2001/002183
    • 2001-10-08
    • TELEFONAKTIEBOLAGET LM ERICSSONERICSSON, TomasHOLMBERG, Per, AndersSTRANDBERG, FredrikWINBERG, LarsLINNERMARK, Nils, Ola
    • ERICSSON, TomasHOLMBERG, Per, AndersSTRANDBERG, FredrikWINBERG, LarsLINNERMARK, Nils, Ola
    • G06F9/38
    • G06F9/4843
    • The read latency caused by job start preparation of a future job is at least partly hidden within the current job by reading information for job start preparation of the future job integrated with the execution of the current job. Instructions for job start preparation are preferably instrumented (701) into the current job and executed (702), whenever possible, in parallel with the instructions of the current job. The integrated job start preparation may include table look-ups, register file updating, instruction fetching and preparation. If the scheduled job order is allowed to change during execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution, it is typically necessary to test (703) whether the next job is still valid before starting the execution of the next job and take appropriate actions (704; 705, 706) dpending on the outcome of the test. In addition to reduced job start preparation time, unused slots in the instruction-parallel execution of the current job may be filled up by the added read instructions, thus providing more efficient utilization of the multiple functional execution units of the processor.
    • 由作业开始准备未来作业引起的读延迟至少部分隐藏在当前作业中,通过阅读与当前作业的执行相集成的未来作业的作业开始准备的信息。 最好将作业开始准备的说明书(701)装入当前作业,并尽可能与当前作业的指令并行执行(702)。 集成作业开始准备可以包括表查找,寄存器文件更新,指令提取和准备。 如果在执行期间允许调度的作业命令改变,则在开始执行之前通常需要测试(703)下一个作业是否仍然有效,通常需要测试(703)下一个作业是否仍然有效 开始执行下一个工作,并对测试结果采取适当的措施(704; 705,706)。 除了减少作业开始准备时间之外,当前作业的指令并行执行中的未使用的插槽可以被添加的读取指令填充,从而提供对处理器的多个功能执行单元的更有效的利用。
    • 5. 发明申请
    • METHOD AND DEVICE FOR MINIMIZING SKEW
    • 用于最小化SKEW的方法和装置
    • WO1994015398A1
    • 1994-07-07
    • PCT/SE1993001088
    • 1993-12-17
    • TELEFONAKTIEBOLAGET LM ERICSSON
    • TELEFONAKTIEBOLAGET LM ERICSSONHOLMBERG, Per, Anders
    • H03K05/00
    • G06F1/10
    • A method and an arrangement for minimizing skew in digital synchronous systems. The arrangement includes N number of driver circuits, each of which has a P number of buffer units, of which each has an input and an output. Each driver circuit has a delay of delta 1, delta 2, delta 3, delta 4 ..., delta N. Of these buffer units, N-1 buffer units are reserved while the inputs of the remaining buffer units P-(N-1) are connected mutually in parallel. The reserved buffer units are used as follows: a signal deriving from a signal source is applied to an input of a first buffer unit in each of the N-number of driver circuits, where the signal is subjected to a delay. The one-time delayed signal from a driver circuit is then delayed once, and only once, in the reserved buffer units of each of the remaining driver circuits. This procedure is repeated for each of the once-delayed signals on the outputs of the first buffer unit in each of the remaining N-1 driver circuits. Output signals which are mutually delayed by a time delay of delta 1+ delta 2+ delta 3+ delta 4 ...+ delta N appear on the outputs of the buffer units in each of the driver circuits, the inputs of these buffer units being connected in parallel.
    • 一种用于最小化数字同步系统中的偏斜的方法和装置。 该装置包括N个驱动器电路,每个驱动器电路具有P个缓冲器单元,其中每个具有输入和输出。 每个驱动器电路具有Δ1,Δ2,Δ3,Δ4 ...,N N的延迟。在这些缓冲器单元中,保留N-1个缓冲器单元,而剩余的缓冲单元P-(N- 1)相互并联连接。 保留的缓冲器单元如下:从信号源导出的信号被施加到N个驱动电路中的每一个中的第一缓冲器单元的输入端,其中信号经受延迟。 然后,驱动器电路的一次性延迟信号在每个剩余驱动电路的保留缓冲器单元中被延迟一次,并且仅延迟一次。 对于剩余的N-1个驱动器电路中的每一个的第一缓冲器单元的输出上的每一次延迟的信号,重复该过程。 在每个驱动器电路中的缓冲器单元的输出端出现输出信号,这些信号相互延迟了delta1 + delta2 + delta3 + delta4 ... + deltaN的时间延迟,这些缓冲单元的输入为 并联连接