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1. 发明申请

WO2002095758A1 DYNAMICALLY CONFIGURATED STORAGE ARRAY WITH IMPROVED DATA ACCESS 审中-公开
标题翻译：具有改进的数据访问的动态配置存储阵列
公开(公告)号：WO2002095758A1
公开(公告)日：2002-11-28
申请号：PCT/US2002/015749
申请日：2002-05-17
申请人： TACHYON SEMICONDUCTOR CORPORATION
发明人： PATTI, Robert
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G06F2211/109 , G11C11/401 , G11C29/42 , G11C29/4401 , G11C29/70 , G11C29/76 , G11C29/846 , G11C2029/0407
摘要： A reconfigurable memory[10, 50, 101, 102, 300] having M bit lines[12] and a plurality of row lines[13], where M>l. The memory includes an array of memory storage cells[15], each memory storage cell[15] storing a data value. The data value is read from or into the storage cells[15] by coupling that data value to one of the bit lines[12] in response to a row control signal on one of the row lines. A row select circuit generates[43] the row control signal on one of the row lines in response to a row address being coupled to the row select circuit[43]. The row select circuit[43] includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address. The memory includes a plurality of sense amplifiers[21], one such sense amplifier being connected to each of the bit lines[13] for measuring a signal value on that bit line. A controller[40, 105, 205, 305] that is part of the memory tests the memory storage cells both at power up and run time to detect defective memory storage cells. The controller[40, 105, 205, 305] uses an error correcting code scheme to detect errors during the actual operation of the memory. The memory includes sufficient spare rows and columns to allow the controller to substitute spares for rows or columns having defective memory storage cells.
摘要翻译：具有M个位线[12]和多个行线[13]的可重构存储器[10,50,101,102,300]，其中M> 1。存储器包括存储存储单元阵列[15]，存储数据值的每个存储器存储单元[15]。响应于行行之一上的行控制信号，将数据值从存储单元[15]读取或写入数据值[15]。响应于行地址耦合到行选择电路[43]，行选择电路在行行之一上生成行控制信号。行选择电路[43]包括用于存储行地址到行行的映射的存储器，其确定为行地址的每个可能值选择行行。存储器包括多个读出放大器[21]，一个这样的读出放大器连接到每个位线[13]，用于测量该位线上的信号值。作为存储器的一部分的控制器[40,105,205,305]在上电和运行时间测试存储器存储单元以检测有缺陷的存储器存储单元。控制器[40,105,205,305]使用纠错码方案在存储器的实际操作期间检测错误。存储器包括足够的备用行和列，以允许控制器将具有缺陷存储器存储单元的行或列替换为备用。

2. 发明申请

WO2002073621A1 MEMORY BASED ON A FOUR-TRANSISTOR STORAGE CELL 审中-公开
标题翻译：基于四晶体存储单元的存储器
公开(公告)号：WO2002073621A1
公开(公告)日：2002-09-19
申请号：PCT/US2002/006564
申请日：2002-03-04
申请人： TACHYON SEMICONDUCTOR CORPORATION
发明人： PATTI, Robert
IPC分类号： G11C11/34
CPC分类号： G11C11/405
摘要： A memory organized as a two-dimensional array of data storage cells (202, 203) having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines (201, 212), one corresponding to each column. The first terminal (108) of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines (211, 213) and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column.
摘要翻译：存储器，其被组织为具有多个行和列的数据存储单元（202,203）的二维阵列。每个数据存储单元具有第一，第二，第三和第四端子，当第三端子处于第一电位时，每个数据存储单元吸收指示存储在其中的电荷的第一和第二端子之间的电流。存储器具有多个位线（201,212），一个对应于每列。当第三终端处于第一电位时，每列中的每个数据存储单元的第一终端（108）连接到与该列对应的位线，并且当第三终端处于第一终端时，每个数据存储单元与该位线断开连接第二个潜力。存储器还包括多个列选择线（211,213）和行选择线。对应于每列和一列与第一列或最后一列相邻的附加列选择行，有一列列选择行。

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