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1. 发明申请

WO2011119500A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：WO2011119500A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/029256
申请日：2011-03-21
申请人： SANDISK IL LTD. , SHARON, Eran , LI, Yan , MOKHLESI, Nima
发明人： SHARON, Eran , LI, Yan , MOKHLESI, Nima
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross- coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同阈值电压进行存储单元的测试。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

2. 发明申请

WO2011080564A1 FLASH MEMORY SYSTEM HAVING CROSS-COUPLING COMPENSATION DURING READ OPERATION 审中-公开
标题翻译：在读取操作期间具有交叉耦合补偿的闪存存储器系统
公开(公告)号：WO2011080564A1
公开(公告)日：2011-07-07
申请号：PCT/IB2010/003338
申请日：2010-12-21
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C11/56 , G11C16/26
CPC分类号： G11C11/5642 , G11C16/26 , G11C16/3422
摘要： A method for reading an addressed cell of a memory system comprises applying at least two different voltage levels to a control gate of a memory cell in an array of memory cells, wherein the memory cell is adjacent to and in electrical field communication with the addressed memory cell. A threshold voltage of the addressed memory cell is measured at each of the at least two different applied voltage levels. At least two of the measured threshold voltages of the addressed memory cell are converted to one or more bit values stored in the addressed memory cell. The bit values are provided to a host of the memory system. An apparatus implementing the method is also disclosed.
摘要翻译：一种用于读取存储器系统的寻址单元的方法包括将至少两个不同的电压电平施加到存储器单元阵列中的存储器单元的控制栅极，其中存储器单元与寻址存储器相邻并且与电场通信细胞。在所述至少两个不同的施加电压电平中的每一个处测量寻址的存储器单元的阈值电压。所寻址的存储器单元的测量阈值电压中的至少两个被转换为存储在所寻址的存储单元中的一个或多个位值。位值被提供给存储器系统的主机。还公开了一种实现该方法的装置。

3. 发明申请

WO2011073710A1 AUXILIARY PARITY BITS FOR DATA WRITTEN IN MULTI-LEVEL CELLS 审中-公开
标题翻译：用于在多级电池中写入数据的辅助奇偶校验位
公开(公告)号：WO2011073710A1
公开(公告)日：2011-06-23
申请号：PCT/IB2009/007789
申请日：2009-12-16
申请人： SANDISK IL LTD , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/1072
摘要： Methods of writing data to and reading data from memory devices and systems for writing and reading data are disclosed. In a particular embodiment, a method includes writing data bits a first time into a memory. Auxiliary parity bits are written in the memory, where the auxiliary parity bits are computed based on the data bits. Subsequent to writing the data bits a first time and writing the auxiliary parity bits, the data bits are written a second time into the memory. Writing the data bits the first time and writing the data bits the second time are directed to one or more storage elements at a common physical address in the memory. Subsequent to writing the data bits the second time, the auxiliary parity bits are discarded while maintaining the data bits in the memory.
摘要翻译：公开了将数据写入和读取数据的方法，用于从存储器件和系统读取和读取数据。在特定实施例中，一种方法包括将数据位第一次写入存储器。辅助奇偶校验位写入存储器中，其中辅助奇偶校验位基于数据位计算。在第一次写入数据位并写入辅助奇偶校验位之后，将数据位第二次写入存储器。第一次写入数据位并且第二次写入数据位将被引导到存储器中公共物理地址的一个或多个存储元件。在第二次写数据位之后，辅助奇偶校验位被丢弃，同时保持存储器中的数据位。

4. 发明申请

WO2011161622A1 OPTIMIZED FLASH MEMORY WITHOUT DEDICATED PARITY AREA AND WITH REDUCED ARRAY SIZE 审中-公开
标题翻译：优化的闪存，没有专用的区域和减少的阵列大小
公开(公告)号：WO2011161622A1
公开(公告)日：2011-12-29
申请号：PCT/IB2011/052706
申请日：2011-06-21
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan , LITSYN, Simon
发明人： SHARON, Eran , ALROD, Idan , LITSYN, Simon
IPC分类号： G11C11/56 , G06F11/10 , G11C16/10
CPC分类号： G06F12/0246 , G06F11/1072 , G06F11/1076 , G11C7/1006 , G11C11/5628 , G11C16/10 , G11C29/00 , G11C2211/5641 , H03M13/05
摘要： A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.
摘要翻译：一种用于优化闪存而没有专用奇偶校验区和减小阵列大小的方法和系统。多级单元（MLC）闪存的存储器容量减小，控制器操作简化。简化操作包括控制器能够将每个主机数据页面编程为整数个闪存页面。在闪存设备中维护每个单元（IBPC）的最大可用信息位，同时还使闪存的编程吞吐量最大化。特性包括动态选择闪存单元使用哪些单元状态的能力。

5. 发明申请

WO2008129534A1 ADAPTIVE DYNAMIC READING OF FLASH MEMORIES 审中-公开
标题翻译：闪存的自适应动态读取
公开(公告)号：WO2008129534A1
公开(公告)日：2008-10-30
申请号：PCT/IL2008/000507
申请日：2008-04-14
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan , SHLICK, Marc
发明人： SHARON, Eran , ALROD, Idan , SHLICK, Marc
IPC分类号： G11C16/28 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C2211/5634
摘要： Each of a plurality of flash memory cells is programmed to a respective one of L≥2 threshold voltage states within a threshold voltage window. A histogram is constructed by determining how many of some or all of the cells have threshold voltages in each of two or more of m≥2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on estimated values of shape parameters of the histogram. Alternatively, the cells are read relative to reference voltages that define m≥2 threshold voltage intervals that span the threshold voltage window, to determine numbers of at least a portion of the cells whose threshold voltages are in each of two or more of the threshold voltage intervals. Respective threshold voltage states are assigned to the cells based on the numbers without re-reading the cells.
摘要翻译：多个闪存单元中的每一个被编程为阈值电压窗口内的L = 2个阈值电压状态中的相应一个。通过确定在阈值电压窗口内的两个或多个m = 2阈值电压间隔中的每一个中的一些或全部单元中有多少个具有阈值电压来构造直方图。基于直方图的形状参数的估计值来选择用于读取单元的参考电压。或者，相对于限定跨越阈值电压窗口的m = 2个阈值电压间隔的参考电压读取单元，以确定阈值电压处于阈值电压中的两个或更多个阈值电压中的每一个中的至少一部分单元的数量间隔。基于数字将各个阈值电压状态分配给单元，而不重新读取单元。

6. 发明申请

WO2012087815A1 NON-VOLATILE MEMORY AND METHODS WITH SOFT-BIT READS WHILE READING HARD BITS WITH COMPENSATION FOR COUPLING 审中-公开
标题翻译：非易失性存储器和采用软读取读取硬件位置并进行补偿的方法
公开(公告)号：WO2012087815A1
公开(公告)日：2012-06-28
申请号：PCT/US2011/065461
申请日：2011-12-16
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , MOKHLESI, Nima
发明人： ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , MOKHLESI, Nima
IPC分类号： G11C11/56 , G11C16/26 , G06F11/10
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as "Direct-Lookahead (DLA)".
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

7. 发明申请

WO2008078314A1 FLASH MEMORY DEVICE, SYSTEM AND METHOD WITH RANDOMIZING FOR SUPPRESSING ERROR 审中-公开
标题翻译：闪存存储器件，用于抑制误差的随机化的系统和方法
公开(公告)号：WO2008078314A1
公开(公告)日：2008-07-03
申请号：PCT/IL2007/001514
申请日：2007-12-06
申请人： SANDISK IL LTD , SHARON, Eran , ALROD, Eran
发明人： SHARON, Eran , ALROD, Eran
IPC分类号： G11C16/04 , G11C16/34 , G11C7/10
CPC分类号： G11C16/0483 , G11C7/1006 , G11C11/5621 , G11C16/3418
摘要： A device and method for storing data includes a nonvolatile memory and a controller and/or circuitry that randomize original data to be stored in the memory while preserving the size of the original data, that store the original data in the memory, and that, in response to a request for the original data, retrieve, derandomize and export the original data without authenticating the requesting entity. A system and method for storing data includes a first nonvolatile memory and a processor that similarly stores data in the first nonvolatile memory by executing driver code stored in a second nonvolatile memory. EEC encloding is applied either before or after randomizing; correspondingly, EEC decoding is applied either after or before derandomizing.
摘要翻译：用于存储数据的设备和方法包括非易失性存储器和随机化要存储在存储器中的原始数据的控制器和/或电路，同时保留将原始数据存储在存储器中的原始数据的大小，并且在响应原始数据的请求，检索，脱机和导出原始数据，而不对请求实体进行验证。用于存储数据的系统和方法包括通过执行存储在第二非易失性存储器中的驱动程序代码，将第一非易失性存储器和处理器类似地存储在第一非易失性存储器中的数据。随机分组前后应用EEC包围; 相应地，EEC解码应用于脱机之前或之后。

8. 发明申请

WO2012087803A2 NON-VOLATILE MEMORY AND METHODS WITH READING SOFT BITS IN NON UNIFORM SCHEMES 审中-公开
标题翻译：非易失性存储器和非均匀程序读取软件位置的方法
公开(公告)号：WO2012087803A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/065429
申请日：2011-12-16
申请人： SANDISK IL LTD. , ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
发明人： ALROD, Idan , SHARON, Eran , MIWA, Toru , HEMINK, Gerrit Jan , KOH, Yee Lih
IPC分类号： G11C11/56
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2029/0411
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

9. 发明申请

WO2012020278A1 DATA CODING USING DIVISIONS OF MEMORY CELL STATES 审中-公开
标题翻译：使用存储器状态部分的数据编码
公开(公告)号：WO2012020278A1
公开(公告)日：2012-02-16
申请号：PCT/IB2010/002245
申请日：2010-09-09
申请人： SANDISK IL LTD. , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/26 , H03M13/09
CPC分类号： G11C7/1006 , G06F12/0246 , G11C11/5642 , G11C16/10 , G11C16/26
摘要： Data storage devices and methods to encode and decode data using divisions of memory cell states are disclosed. A method includes dividing data bits into disjoint multiple groups of data bits and storing the data bits into a plurality of memory cells. The storing is done by setting each of the plurality of memory cells to a corresponding state selected from at least three ordered states. For each of the multiple groups of data bits, when a request is received for reading a particular group of the data bits, the request is serviced by selecting a disjoint division of the at least three ordered states of the memory cells into a first set of states and a second set of states. Each of the states in the first set of states has a higher position than any of the states in the second set of states according to the order of the states. For each cell of the plurality of memory cells, a determination is made whether the cell is in the first set of states or the second set of states. Based on the determination, the particular group of the data bits is generated in response to the request for reading the particular group of the data bits without use of additional data that depends upon a state of one of the memory cells.
摘要翻译：公开了使用存储单元状态的划分对数据进行编码和解码的数据存储设备和方法。一种方法包括将数据位分成不相交的多组数据位并将数据位存储到多个存储单元中。通过将多个存储单元中的每一个设置为从至少三个有序状态中选择的对应状态来进行存储。对于多组数据位中的每一组，当接收到用于读取特定数据位组的请求时，通过选择存储器单元的至少三个有序状态的不相交分割为第一组状态和第二组状态。根据状态的顺序，第一组状态中的每个状态具有比第二组状态中的任何状态更高的位置。对于多个存储器单元中的每个单元，确定单元是处于第一组状态还是第二组状态。基于该确定，响应于读取特定数据位组的请求而生成数据位的特定组，而不使用取决于存储器单元之一的状态的附加数据。

10. 发明申请

WO2010001383A1 METHOD FOR SCRAMBLING DATA STORED IN NON-VOLATILE MEMORY USING SCRAMBLER SEEDS BASED ON PAGE AND BLOCK NUMBERS 审中-公开
标题翻译：使用基于页面和块号的SCRAMBLER种子来筛选存储在非易失性存储器中的数据的方法
公开(公告)号：WO2010001383A1
公开(公告)日：2010-01-07
申请号：PCT/IL2009/000629
申请日：2009-06-24
申请人： SANDISK IL LTD , SHARON, Eran , ALROD, Idan
发明人： SHARON, Eran , ALROD, Idan
IPC分类号： G11C7/10 , G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C7/1006 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated using a seed based on the page number of a page of the memory device to which the data is to be written, to provide first scrambled data, which is scrambled using a second pseudo random number which is generated using a seed based on the block number of a block of the memory device to which the data is to be written. This avoids bit lme-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled using a third pseudo random number whose seed depends on the section number of a section within a page. Scrambling may also be based on one or more previous pages which were written.
摘要翻译：一种用于对存储器件中读取错误减少的数据进行编程和读取的方法和系统。在一种方法中，使用基于要写入数据的存储器件的页面的页码使用种子生成的第一伪随机数来加扰要写入存储器件的日期，以提供第一加密数据，其使用基于要写入数据的存储器件的块的块号使用种子生成的第二伪随机数进行加扰。这样可以避免可能导致读取错误的位对位线和块到块冗余。数据也可以使用第三伪随机数进行加扰，其种子取决于页面内部分的段号。加扰也可以基于一个或多个先前的页面。

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