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1. 发明申请

WO2017208014A1 A MEMORY UNIT 审中-公开
标题翻译：内存单元
公开(公告)号：WO2017208014A1
公开(公告)日：2017-12-07
申请号：PCT/GB2017/051591
申请日：2017-06-02
申请人： SURECORE LIMITED
发明人： COSEMANS, Stefan , ROOSELEER, Bram
IPC分类号： G11C8/08 , G11C8/12 , G11C11/418
摘要： There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.
摘要翻译：提供了一种存储器单元，其包括存储器单元阵列和被配置为输出寻址存储器单元阵列的一部分/子集的输出地址信号的驱动器电路。所述驱动器电路包括逻辑门，所述逻辑门经配置以接收一个或一个以上输入地址信号且根据所述一个或一个以上输入地址信号提供输出地址信号，且其中所述逻辑门经配置以输出由当逻辑门的输出为真/高时，将一个或多个输入地址信号中的第一个作为输出地址信号。

2. 发明申请

WO2017149282A1 MULTIPLE DATA RATE MEMORY 审中-公开
标题翻译：多数据速率记忆
公开(公告)号：WO2017149282A1
公开(公告)日：2017-09-08
申请号：PCT/GB2017/050524
申请日：2017-02-27
申请人： SURECORE LIMITED
发明人： COSEMANS, Stefan
IPC分类号： G11C7/22 , G11C7/10 , G11C8/18 , G11C11/419 , G11C11/418
摘要： There is provided a multiple data rate memory comprising a clock splitting circuit and a multiplexing address latch. The clock splitting circuit is configured to generate first and second internal clock pulses from a rising edge of an external clock signal and to provide the first and second internal clock signals to the multiplexing address latch. The multiplexing address latch is configured to output a first address signal in response to the first internal clock pulse and a second address signal in response to the second internal clock pulse.
摘要翻译：提供了一种包括时钟分离电路和多路复用地址锁存器的多数据速率存储器。时钟分离电路被配置为从外部时钟信号的上升沿产生第一和第二内部时钟脉冲，并将第一和第二内部时钟信号提供给复用地址锁存器。多路复用地址锁存器被配置为响应于第一内部时钟脉冲输出第一地址信号，并响应于第二内部时钟脉冲输出第二地址信号。

3. 发明申请

WO2017208016A1 MEMORY UNIT 审中-公开
标题翻译：记忆单元
公开(公告)号：WO2017208016A1
公开(公告)日：2017-12-07
申请号：PCT/GB2017/051593
申请日：2017-06-02
申请人： SURECORE LIMITED
发明人： COSEMANS, Stefan , ROOSELEER, Bram
IPC分类号： G11C11/419 , G11C7/18 , G11C7/12 , G11C5/14 , G11C8/12 , G11C8/10 , G11C11/418
CPC分类号： G11C11/419 , G11C5/145 , G11C7/12 , G11C7/18 , G11C8/10 , G11C8/12 , G11C11/418 , G11C2207/005
摘要： There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.
摘要翻译：提供了一种用于访问作为存储器单元的一部分的多个存储器单元的存储器单元的方法，所述存储器单元被分组为多个存储器单元组，其中每个存储器单元组与一个或多个局部位线相关联，所述一个或多个局部位线中的每一个经由包括PMOS晶体管的传输门可操作地连接到对应的全局位线。该方法包括通过将施加到对应的PMOS晶体管的栅极的栅极电压减小到足以允许PMOS晶体管导通的值来将一个或多个局部位线中的每一个连接到对应的全局位线，其中足以使PMOS晶体管导通的栅极电压的值是正电压或负电压。

4. 发明申请

WO2017149295A1 MULTIPLE DATA RATE MEMORY 审中-公开
标题翻译：多数据速率记忆
公开(公告)号：WO2017149295A1
公开(公告)日：2017-09-08
申请号：PCT/GB2017/050540
申请日：2017-02-28
申请人： SURECORE LIMITED
发明人： COSEMANS, Stefan , ROOSELEER, Bram
IPC分类号： G11C11/419 , G11C7/06 , G11C7/08 , G11C7/12 , G11C7/10 , G11C8/16 , G11C7/22 , G11C7/18
摘要： There is provided a multiple data rate memory configured to implement first and second memory accesses within a single cycle of an external clock signal. The memory comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to at least one local bit line, the at least one local bit line of each memory cell group being connected to a local-to-global interface circuit. The local-to- global interface circuit is configured to control the state of at least one first global bit line in dependence upon the state of the at least one local bit line during the first memory access and to control the state of at least one second global bitline in dependence upon the state of the at least one local bit line during the second memory access.
摘要翻译：提供了一种多数据速率存储器，其被配置为在外部时钟信号的单个周期内实现第一和第二存储器访问。存储器包括多个存储单元组，每个存储单元组包括多个存储单元，每个存储单元可操作地连接到至少一个本地位线，每个存储单元组的至少一个本地位线连接到本地全球接口电路。局部到全局接口电路被配置成根据第一存储器访问期间至少一条局部位线的状态来控制至少一条第一全局位线的状态，并控制至少一条第二全局位线的状态全局位线取决于在第二次存储器访问期间至少一条局部位线的状态。

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