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1. 发明申请

WO2018148549A1 METHODS FOR ASSESSING SEMICONDUCTOR STRUCTURES 审中-公开
公开(公告)号：WO2018148549A1
公开(公告)日：2018-08-16
申请号：PCT/US2018/017629
申请日：2018-02-09
申请人： SUNEDISON SEMICONDUCTOR LIMITED
发明人： KOMMU, Srikanth , PEIDOUS, Igor , WANG, Gang , LIBBERT, Jeffrey L. , RAPOPORT, Igor
IPC分类号： H01L21/66 , G01R31/26
摘要： Methods for assessing the quality of a semiconductor structure having a charge trapping layer (CTL) to, for example, determine if the structure is suitable for use as a radiofrequency device are disclosed. Embodiments of the assessing method may involve measuring an electrostatic parameter at an initial state and at an excited state in which charge carriers are generated.

2. 发明申请

WO2016140850A1 METHOD OF DEPOSITING CHARGE TRAPPING POLYCRYSTALLINE SILICON FILMS ON SILICON SUBSTRATES WITH CONTROLLABLE FILM STRESS 审中-公开
标题翻译：在具有可控薄膜应力的硅基底上沉积电荷捕获多晶硅薄膜的方法
公开(公告)号：WO2016140850A1
公开(公告)日：2016-09-09
申请号：PCT/US2016/019464
申请日：2016-02-25
申请人： SUNEDISON SEMICONDUCTOR LIMITED , LIBBERT, Jeffrey Louis
发明人： LIBBERT, Jeffrey Louis , WANG, Gang , THOMAS, Shawn G. , PEIDOUS, Igor
IPC分类号： H01L21/02 , H01L21/763 , H01L21/762
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02513 , H01L21/02532 , H01L21/02639 , H01L21/76251 , H01L21/76254 , H01L21/763
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.
摘要翻译：提供了半导体绝缘体多层结构。多层包括高电阻率单晶半导体处理衬底，织构氧化物，氮化物或氧氮化物层，多晶硅层，电介质层和单晶半导体器件层。以减少晶片弓的方式制备多层结构。

3. 发明申请

WO2016036317A1 HIGH RESISTIVITY SILICON-ON-INSULATOR WAFER MANUFACTURING METHOD FOR REDUCING SUBSTRATE LOSS 审中-公开
标题翻译：用于减少基板损耗的高电阻率硅绝缘体制造方法
公开(公告)号：WO2016036317A1
公开(公告)日：2016-03-10
申请号：PCT/SG2015/050299
申请日：2015-09-04
申请人： SUNEDISON SEMICONDUCTOR LIMITED
发明人： LIU, Qingmin , WANG, Gang
IPC分类号： H01L21/762
CPC分类号： H01L29/66833 , H01L21/02381 , H01L21/02428 , H01L21/0254 , H01L21/02598 , H01L21/304 , H01L21/324 , H01L21/76254 , H01L21/763 , H01L29/2003 , H01L29/205 , H01L29/4234 , H01L29/517 , H01L29/518 , H01L29/792
摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer.
摘要翻译：提供了一种多层复合结构体及其制备方法。多层复合结构包括具有至少约500欧姆 - 厘米的最小体积电阻率的半导体处理衬底; 与半导体处理衬底接触的半导体氮化物层，选自氮化铝，氮化硼，氮化铟，氮化镓，氮化镓铝，氮化镓铟氮化镓，铝镓铟氮化硼的氮化物半导体层和其组合; 与所述半导体氮化物层接触的电介质层; 以及与电介质层接触的半导体器件层。

4. 发明申请

WO2015112308A1 HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF 审中-公开
标题翻译：高电阻SOI波形及其制造方法
公开(公告)号：WO2015112308A1
公开(公告)日：2015-07-30
申请号：PCT/US2014/072546
申请日：2014-12-29
申请人： SUNEDISON SEMICONDUCTOR LIMITED , PEIDOUS, Igor
发明人： PEIDOUS, Igor , KOMMU, Srikanth , WANG, Gang , THOMAS, Shawn G.
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/76254
摘要： A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si 1-x Ge x , Si 1-x C x , Si 1-x-y Ge x Sn y , Si 1-x-y-z Ge x Sn y C z , Ge 1-x Sn x , group IIIA-nitrides, semiconductor oxides, and any combination thereof.
摘要翻译：提供了用于制造SOI结构的高电阻率单晶半导体手柄结构。手柄结构包括在处理衬底和掩埋氧化物层之间的中间半导体层。中间半导体层包括多晶，非晶，纳米晶体或单晶结构，并且包括选自Si1-xGex，Si1-xCx，Si1-x-yGexSny，Si1-xy-zGexSnyCz，Ge1-xSnx， IIIA-氮化物，半导体氧化物及其任何组合。

5. 发明申请

WO2016196011A1 A METHOD OF MANUFACTURING SILICON GERMANIUM-ON-INSULATOR 审中-公开
标题翻译：一种制造硅绝缘体的方法
公开(公告)号：WO2016196011A1
公开(公告)日：2016-12-08
申请号：PCT/US2016/033097
申请日：2016-05-18
申请人： SUNEDISON SEMICONDUCTOR LIMITED , THOMAS, Shawn G.
发明人： THOMAS, Shawn G. , WANG, Gang
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76251 , H01L21/0242 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/3065
摘要： The disclosed method is suitable for producing a SiGe-on-insulator structure. According to some embodiments of the method, a layer comprising SiGe is deposited on silicon-on-insulator substrate comprising an ultra-thin silicon top layer. In some embodiments, the layer comprising SiGe is deposited by epitaxial deposition. In some embodiments, the SiGe epitaxial layer is high quality since it is produced by engineering the strain relaxation at the Si/buried oxide interface. In some embodiments, the method accomplishes elastic strain relaxation of SiGe grown on a few monolayer thick Si layer that is weakly bonded to the underline oxide.
摘要翻译：所公开的方法适用于制造绝缘体上的SiGe结构。根据该方法的一些实施例，包括SiGe的层被沉积在包括超薄硅顶层的绝缘体上的衬底上。在一些实施例中，通过外延沉积沉积包含SiGe的层。在一些实施例中，SiGe外延层是高质量的，因为其通过在Si /掩埋氧化物界面处工程化应变松弛而产生。在一些实施方案中，该方法实现了在与下划线氧化物弱结合的少量单层厚Si层上生长的SiGe的弹性应变弛豫。

6. 发明申请

WO2016081356A1 HIGH RESISTIVITY SEMICONDUCTOR-ON-INSULATOR WAFER AND A METHOD OF MANUFACTURING 审中-公开
标题翻译：高电阻半导体绝缘体波形及其制造方法
公开(公告)号：WO2016081356A1
公开(公告)日：2016-05-26
申请号：PCT/US2015/060854
申请日：2015-11-16
申请人： SUNEDISON SEMICONDUCTOR LIMITED , PEIDOUS, Igor
发明人： PEIDOUS, Igor , FEI, Lu , LIBBERT, Jeffrey Louis , JONES, Andrew M. , USENKO, Alex , WANG, Gang , THOMAS, Shawn G. , KOMMU, Srikanth
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.
摘要翻译：提供了半导体绝缘体多层结构。多层包括高电阻率单晶半导体处理衬底，包括硅，锗或硅锗的任选松弛的半导体层，可选的多晶硅层，电介质层和单晶半导体器件层。

7. 发明申请

WO2017087393A1 MANUFACTURING METHOD OF SMOOTHING A SEMICONDUCTOR SURFACE 审中-公开
标题翻译：平滑半导体表面的制造方法
公开(公告)号：WO2017087393A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/062050
申请日：2016-11-15
申请人： SUNEDISON SEMICONDUCTOR LIMITED , LOTTES, Charles, R.
发明人： LOTTES, Charles, R. , WANG, Gang , KWESKIN, Sasha
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76254 , H01L21/3247
摘要： A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30um X 30um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.
摘要翻译：提供了一种用于制备半导体结构（例如，绝缘体上半导体结构）的方法，该方法包括具有光滑表面的器件层。所提供的方法涉及通过在升高的温度下利用应力增强的表面扩散来平滑半导体衬底表面。该方法的目的是达到原子级表面光滑度（例如，在根据30um X 30um AFM测量的均方根测量的在1.0和1.5埃之间的范围内的光滑度），这是先进的（次28 nm）CMOS器件制造。

8. 发明申请

WO2017059114A1 CVD APPARATUS 审中-公开
标题翻译： CVD装置
公开(公告)号：WO2017059114A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/054507
申请日：2016-09-29
申请人： SUNEDISON SEMICONDUCTOR LIMITED , THOMAS, Shawn George
发明人： THOMAS, Shawn George , WANG, Gang
IPC分类号： C23C16/458
CPC分类号： C23C16/4585
摘要： A preheat ring (126) for use in a chemical vapor deposition system includes a first portion and a second portion selectively coupled to the first portion such that the first and second portions combine to form an opening configured to receive a susceptor therein. Each of the first and second portions is independently moveable with respect to each other.
摘要翻译：用于化学气相沉积系统的预热环（126）包括第一部分和第二部分，第一部分和第二部分选择性地联接到第一部分，使得第一部分和第二部分组合以形成构造成在其中接收基座的开口。第一和第二部分中的每一个可独立地相对于彼此移动。

9. 发明申请

WO2016196060A1 A METHOD OF MANUFACTURING SEMICONDUCTOR-ON-INSULATOR 审中-公开
标题翻译：制造半导体绝缘体的方法
公开(公告)号：WO2016196060A1
公开(公告)日：2016-12-08
申请号：PCT/US2016/033780
申请日：2016-05-23
申请人： SUNEDISON SEMICONDUCTOR LIMITED , THOMAS, Shawn G.
发明人： THOMAS, Shawn G. , WANG, Gang
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/0262 , H01L21/30604 , H01L21/3065
摘要： The disclosed method is suitable for producing a semiconductor-on-insulator structure, such as a Ge(Si)-on-insulator structure or a Ge-on-insulator structure. According to the method, a multilayer comprising alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer is completed with a silicon passivation layer. A cleave plane is formed within the multilayer, and the multilayer structure is bonded to a handle substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleave plane to thereby prepare a semiconductor-on-insulator structure comprising a semiconductor handle substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating pairs of layers, comprising a layer of silicon and a layer of germanium optionally with silicon.
摘要翻译：所公开的方法适用于制造诸如Ge（Si） - 绝缘体结构或绝缘体上Ge结构的绝缘体上半导体结构。根据该方法，在包括锗缓冲层的硅衬底上沉积包括交替成对层的多层，其包括硅层和任选地与硅的锗层。多层完成了硅钝化层。在多层内形成解理面，多层结构体与包含电介质层的手柄基板结合。多层结构沿着解理面切割，由此制备绝缘体上半导体结构，其包括半导体处理衬底，电介质层，硅钝化层以及至少一部分交替层，包括一层硅和一层锗，任选地具有硅。

10. 发明申请

WO2016109502A1 PREPARATION OF SILICON-GERMANIUM-ON-INSULATOR STRUCTURES 审中-公开
标题翻译：硅 - 绝缘体结构的制备
公开(公告)号：WO2016109502A1
公开(公告)日：2016-07-07
申请号：PCT/US2015/067816
申请日：2015-12-29
申请人： SUNEDISON SEMICONDUCTOR LIMITED , THOMAS, Shawn George
发明人： THOMAS, Shawn George , WANG, Gang
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L21/76243 , H01L21/76262 , H01L21/76829
摘要： Donor structures having a germanium buffer layer for preparing silicon-germanium-on-insulator structures by layer transfer are disclosed. Bonded structures and methods for preparing silicon-germanium-on-insulator structures by a layer transfer method are also disclosed.
摘要翻译：公开了具有用于通过层转移制备绝缘体上硅锗结构的锗缓冲层的供体结构。还公开了通过层转移方法制备绝缘体上硅结构的结合结构和方法。

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