专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007006505A1 SEMICONDUCTOR POWER DEVICE WITH MULTIPLE DRAIN STRUCTURE AND CORRESPONDING MANUFACTURING PROCESS 审中-公开
标题翻译：具有多个排水结构和相应制造工艺的半导体功率器件
公开(公告)号：WO2007006505A1
公开(公告)日：2007-01-18
申请号：PCT/EP2006/006673
申请日：2006-07-07
申请人： STMICROELECTRONICS S.R.L. , SAGGIO, Mario, Giuseppe , FRISINA, Ferruccio , RASCUNA, Simone
发明人： SAGGIO, Mario, Giuseppe , FRISINA, Ferruccio , RASCUNA, Simone
IPC分类号： H01L21/336 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712
摘要： Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity whereon a drain semiconductor layer (20) is formed, characterised in that it comprises the following steps: forming at least a first semiconductor epitaxial layer (21) of the first type of conductivity forming the drain epitaxial layer (20) on the semiconductor substrate (100) , forming first sub-regions (51) of a second type of conductivity by means of a first selective implant step forming second sub-regions (Dl, DIa) of the first type of conductivity by means of a second implant step forming a surface semiconductor layer (23) wherein body regions (40) of the second type of conductivity are formed being aligned with the first sub-regions (51) , carrying out a thermal diffusion process so that the first sub-regions (51) form a single electrically continuous column region (50) being aligned and in electric contact with the body regions (40).
摘要翻译：一种集成在形成有漏极半导体层（20）的第一导电类型的半导体衬底（100）上的多漏极功率电子器件（30）的制造方法，其特征在于包括以下步骤：至少形成在所述半导体衬底（100）上形成所述漏极外延层（20）的所述第一导电类型的第一半导体外延层（21），通过第一选择性形成第二导电类型的第一子区域（51）植入步骤通过形成表面半导体层（23）的第二注入步骤形成第一类型导电性的第二子区域（D1，DIa），其中形成第二导电类型的主体区域（40）与所述第一子区域（51）进行热扩散处理，使得所述第一子区域（51）形成与所述主体区域（40）电接触的单个电连续列区域（50）。

2. 发明申请

WO2007006503A1 SEMICONDUCTOR POWER DEVICE WITH MULTIPLE DRAIN AND CORRESPONDING MANUFACTURING PROCESS 审中-公开
标题翻译：具有多个漏极和相应制造工艺的半导体功率器件
公开(公告)号：WO2007006503A1
公开(公告)日：2007-01-18
申请号：PCT/EP2006/006671
申请日：2006-07-07
申请人： STMICROELECTRONICS S.R.L. , SAGGIO, Mario, Giuseppe , FRISINA, Ferruccio , RASCUNA, Simone
发明人： SAGGIO, Mario, Giuseppe , FRISINA, Ferruccio , RASCUNA, Simone
IPC分类号： H01L21/336 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0886 , H01L29/1095 , H01L29/66712
摘要： Process for manufacturing a power electronic device (30) comprising the following steps: forming a first semiconductor layer (21) of the first type of conductivity forming at least a second semiconductor layer (22) of a second type of conductivity value on the first semiconductor layer (21), forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity forming, above said at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity, forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of semiconductor layer (22) free from the plurality of said at least second implanted regions (D1), carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D).
摘要翻译：一种用于制造功率电子器件（30）的方法，包括以下步骤：形成第一类型的导电性的第一半导体层（21），其形成至少第二类型的电导率值的第二半导体层（22），其在第一半导体在所述至少第二半导体层（22）中形成所述第一类型的导电形成的第一多个注入区域（D1），在所述至少第二半导体层（22）之上，表面（21），表面在所述表面半导体层（26）中形成所述第一导电类型的半导体层（26），所述半导体层（26）在所述第二导电类型的主体区域（40）中形成，所述主体区域（40）与半导体层从所述多个所述至少第二注入区域（D1）中，进行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续的注入区域（D）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式