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1. 发明申请

WO2012083147A3 SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING 审中-公开
标题翻译：自对准NAND闪存选择门字幕用于双面格式
公开(公告)号：WO2012083147A3
公开(公告)日：2012-10-04
申请号：PCT/US2011065442
申请日：2011-12-16
申请人： SPANSION LLC , CHEN TUNG-SHENG , FANG SHENQING
发明人： CHEN TUNG-SHENG , FANG SHENQING
IPC分类号： H01L21/027
CPC分类号： H01L21/302 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11565 , H01L27/1157
摘要： A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.
摘要翻译：公开了一种用于双重图案化的方法。在一个实施例中，通过在光致抗蚀剂图案的边缘周围放置间隔图案来开始在多个核心字线的任一侧上形成一对选择栅极字线。将光致抗蚀剂图案剥离留下间隔图案。修剪掩模放置在间隔图案的一部分上。间隔图案的部分被蚀刻掉，不被修剪掩模覆盖。去除修剪掩模，其中间隔图案的第一剩余部分限定多个核心字线。放置焊盘掩模，使得焊盘掩模和间隔物图案的第二剩余部分在多个核心字线的任一侧上限定选择栅极字线。最后，通过使用激光掩模和间隔物图案的第一和第二剩余部分来蚀刻至少一个图案转印层，以将选择栅极字线和多个核心字线蚀刻成多晶硅层。

2. 发明申请

WO2012087978A3 EDGE ROUNDED FIELD EFFECT TRANSISTORS AND METHODS OF MANUFACTURING 审中-公开
标题翻译：边缘圆形场效应晶体管及其制造方法
公开(公告)号：WO2012087978A3
公开(公告)日：2012-09-27
申请号：PCT/US2011065930
申请日：2011-12-19
申请人： SPANSION LLC , FANG SHENQING , CHEN TUNG-SHENG
发明人： FANG SHENQING , CHEN TUNG-SHENG
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/28282 , H01L21/28202 , H01L27/11568 , H01L29/518
摘要： Embodiments of the present technology are directed toward gate sidcwall engineering of field effect transistors. The techniques include formation of a blocking dielectric region and nitridation of a surface thereof. After nitridation of the blocking dielectric region, a gate region is formed thereon and the sidewails of the gate region are oxidized to round off gate sharp corners and reduce the electrical field at the gate comers.
摘要翻译：本技术的实施例针对场效应晶体管的栅极侧壁工程。这些技术包括形成阻挡电介质区域和其表面的氮化。在阻挡电介质区域的氮化之后，在其上形成栅极区域，并且栅极区域的侧向栅极被氧化以围绕栅极尖锐角落并减小栅极端部的电场。

3. 发明申请

WO2012087974A3 PROCESS MARGIN ENGINEERING IN CHARGE TRAPPING FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：电荷捕捉场效应晶体管的过程工程
公开(公告)号：WO2012087974A3
公开(公告)日：2012-08-23
申请号：PCT/US2011065923
申请日：2011-12-19
申请人： SPANSION LLC , CHEN TUNG-SHENG , FANG SHENQING
发明人： CHEN TUNG-SHENG , FANG SHENQING
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/76232 , H01L21/28282 , H01L27/1157 , H01L29/792
摘要： Embodiments of the present technology arc directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers. The second set of nitride layers is oxidized to form a charge trapping region on the tunneling dielectric region and a blocking dielectric region on the charge trapping region. A gate region is then deposited on the blocking dielectric region.
摘要翻译：本技术的实施例针对电荷捕获场效应晶体管的电荷捕获区域工艺裕度工程。这些技术包括在衬底上形成多个浅沟槽隔离区域，其中浅沟槽隔离区域的顶部在衬底上延伸给定量。衬底的一部分被氧化以形成隧道电介质区域。第一组一个或多个氮化物层沉积在隧道电介质区域和浅沟槽隔离区域上，其中第一组氮化物层的厚度约为给定量的一半，即浅沟槽隔离区的顶部在上面延伸底物。第一组氮化物层的一部分被回蚀刻到沟槽隔离区的顶部。在蚀刻后的第一组氮化物层上沉积第二组一个或多个氮化物层。第二组氮化物层被氧化以在隧穿电介质区域上形成电荷捕捉区域，并在电荷俘获区域上形成阻挡电介质区域。然后将栅极区域沉积在阻挡电介质区域上。

4. 发明申请

WO2012092496A3 MEMORY WITH EXTENDED CHARGE TRAPPING LAYER 审中-公开
标题翻译：具有扩展电荷捕获层的存储器
公开(公告)号：WO2012092496A3
公开(公告)日：2013-01-17
申请号：PCT/US2011067905
申请日：2011-12-29
申请人： SPANSION LLC , FANG SHENQING , CHEN TUNG-SHENG , CHEN CHUN
发明人： FANG SHENQING , CHEN TUNG-SHENG , CHEN CHUN
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/4234 , H01L29/792
摘要： A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.
摘要翻译：存储器阵列包括多个位线和多个字线，栅极区域和电荷俘获层。电荷捕获层比字线宽; 电荷捕获层延伸超过栅极区域的边缘以便于捕获和去除电荷。

5. 发明申请

WO2008016487A3 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 审中-公开
标题翻译：具有多个氮化物层的存储器单元系统
公开(公告)号：WO2008016487A3
公开(公告)日：2008-06-05
申请号：PCT/US2007016251
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES INC , XUE LEI , SUGINO RINJI , SUH YOUSEOK , SHIRAIWA HIDEHIKO , DING MENG , FANG SHENQING , JEON JOONG
发明人： XUE LEI , SUGINO RINJI , SUH YOUSEOK , SHIRAIWA HIDEHIKO , DING MENG , FANG SHENQING , JEON JOONG
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system (1200) is provided including forming a first insulator layer (512) over a semiconductor substrate (504), forming a charge trap layer (514) over the first insulator layer (512), forming a second insulator layer (520) over the charge trap layer (514), forming a top blocking intermediate layer (516) over the second insulator layer (520), and forming a contact layer (506) over the top blocking intermediate layer (516).
摘要翻译：提供了一种存储器单元系统（1200），包括在半导体衬底（504）上方形成第一绝缘体层（512），在第一绝缘体层（512）上方形成电荷捕获层（514），形成第二绝缘体层（520 ）在电荷陷阱层（514）上方，在第二绝缘体层（520）上方形成顶部阻挡中间层（516），并且在顶部阻挡中间层（516）上方形成接触层（506）。

6. 发明申请

WO2008016514A2 INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS 审中-公开
标题翻译：集成电路记忆系统采用硅胶层
公开(公告)号：WO2008016514A2
公开(公告)日：2008-02-07
申请号：PCT/US2007016620
申请日：2007-07-24
申请人： ADVANCED MICRO DEVICES INC , SPANSION LLC , JOSHI AMOL RAMESH , SACHAR HARPREET , SUH YOUSEOK , FANG SHENQING , YANG CHIH-YUH , SINGH LOVEJEET , SHIRAIWA HIDEHIKO , CHANG KUO-TUNG , BELL SCOTT A , HOLBROOK ALLISON , TORII SATOSHI , MATSUMOTO DAVID H
发明人： JOSHI AMOL RAMESH , SACHAR HARPREET , SUH YOUSEOK , FANG SHENQING , YANG CHIH-YUH , SINGH LOVEJEET , SHIRAIWA HIDEHIKO , CHANG KUO-TUNG , BELL SCOTT A , HOLBROOK ALLISON , TORII SATOSHI , MATSUMOTO DAVID H
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/762 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system [100] that includes: providing a substrate [102]; forming a silicon rich charge storage layer [204] over the substrate [102]; forming a first isolation trench [400] through the silicon rich charge storage layer [204] in a first direction [900]; and forming a second isolation trench [800] through the silicon rich charge storage layer [204] in a second direction [902].
摘要翻译：一种集成电路存储器系统，包括：提供衬底[102]; 在衬底[102]上形成富硅电荷存储层[204]。在第一方向上通过富硅电荷存储层[204]形成第一隔离沟槽[400]; 以及在第二方向上通过富硅电荷存储层[204]形成第二隔离沟槽[800]。

7. 发明申请

WO2014093654A3 PROCESS CHARGING PROTECTION FOR SPLIT GATE CHARGE TRAPPING FLASH 审中-公开
标题翻译：分裂栅极电荷陷阱闪光的过程充电保护
公开(公告)号：WO2014093654A3
公开(公告)日：2014-10-23
申请号：PCT/US2013074732
申请日：2013-12-12
申请人： SPANSION LLC
发明人： CHEN CHUN , HADDAD SAMEER , CHANG KUO TUNG , RAMSBEY MARK , KIM UNSOON , FANG SHENQING
IPC分类号： H01L29/78 , H01L21/336 , H01L27/115
CPC分类号： H01L29/792 , H01L27/0255 , H01L27/0292 , H01L27/11563 , H01L27/1157 , H01L27/11573 , H01L29/42344
摘要： A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.
摘要翻译：这里给出了一种半导体器件和制造这种器件的方法。该半导体器件包括多个存储单元，多个p-n结以及第一金属层的金属迹线。多个存储器单元中的每一个包括布置在第一电介质上的第一栅极，布置在第二电介质上并且与第一栅极的侧壁相邻的第二栅极，在衬底中与第一栅极相邻的第一掺杂区域以及在与所述第二栅极相邻的所述衬底中的第二掺杂区域。多个p-n结与每个存储器单元的掺杂区域电隔离。金属迹线沿通孔到多个存储器单元中的至少一个存储器单元的第二栅极之间的单个平面以及到多个pn结中的p-n结的通孔延伸。

8. 发明申请

WO2014093647A1 THREE DIMENSIONAL CAPACITOR 审中-公开
标题翻译：三维电容器
公开(公告)号：WO2014093647A1
公开(公告)日：2014-06-19
申请号：PCT/US2013074713
申请日：2013-12-12
申请人： SPANSION LLC
发明人： RAMSBEY MARK , KIM UNSOON , CHANG KUO TUNG , CHEN CHUN , FANG SHENQING
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/0805 , H01L28/91 , H01L28/92
摘要： Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application.
摘要翻译：提供集成电容器结构及其制造方法。在一个实施例中，集成电容器结构利用可以在垂直于衬底的平面中形成的电容，产生三维电容器结构。这允许在相对较小的衬底区域上形成具有较高电容的集成电容器结构。实施例适用于电荷泵，并且可以被制造成具有根据应用期望的更多或更小的电容。

9. 发明申请

WO2014078795A8 METHOD TO IMPROVE CHARGE TRAP FLASH MEMORY CORE CELL PERFORMANCE AND RELIABILITY 审中-公开
标题翻译：改进电荷捕捉闪存存储器核心单元性能和可靠性的方法
公开(公告)号：WO2014078795A8
公开(公告)日：2014-08-14
申请号：PCT/US2013070579
申请日：2013-11-18
申请人： SPANSION LLC
发明人： CHEN TUNG-SHENG , FANG SHENQING
IPC分类号： H01L27/115
CPC分类号： H01L29/513 , H01L21/28282 , H01L21/3081 , H01L21/762 , H01L21/76232 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
摘要翻译：一种在充电捕获NAND和NOR闪存中提供高质量底部氧化物层和顶部氧化物层的半导体处理方法。 NAND和NOR闪存的底部氧化物层和顶部氧化物层均决定阵列器件的性能和可靠性。该方法描述了克服了使用预沉积富硅氮化物的传统氧化方法导致的角部变薄问题和差的顶部氧化物质量。

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