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1. 发明申请

WO2003023849A1 MICROELECTRONIC MECHANICAL SYSTEM AND METHODS 审中-公开
标题翻译：微电子机械系统与方法
公开(公告)号：WO2003023849A1
公开(公告)日：2003-03-20
申请号：PCT/US2002/027822
申请日：2002-08-29
申请人： SILICON LIGHT MACHINES
发明人： BRUNER, Mike
IPC分类号： H01L23/02
CPC分类号： B81C1/00484 , B81B2201/0271 , B81B2203/0136 , B81C1/00246 , B81C1/00333 , B81C2201/0109 , B81C2201/014 , B81C2203/0136 , B81C2203/0735
摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer (211) that preferably comprises silicon oxide and/or silicon nitride and which is formed over an etch resistant substrate (203). A patterned device layer (206), preferably comprising silicon nitride, is embedded in a sacrificial material (205, 209), preferably comprising polysilicon, and is disposed between the etch resistant substrate (203) and the capping layer (211). Access trenches or holes (219) are formed into the capping layer (211) and the sacrificial material (205, 209) is selectively etched through the access trenches (219) such that portions of the device layer (206) are released from the sacrificial material (205, 209). The etchant preferably comprises a noble gas fluoride N g F 2x (wherein Ng = Xe, Kr or Ar: and where x = 1, 2 or 3). After etching that sacrificial material (205, 209), the access trenches (219) are sealed to encapsulate (241) released portions the device layer (206) between the etch resistant substrate (203) and the capping layer (211). The current invention is particularly useful for fabricating MEMs devices, multiple cavity devices and devices with multiple release features.
摘要翻译：本发明提供了包封的释放结构，其中间体及其制备方法。多层结构具有优选包括氧化硅和/或氮化硅并且形成在耐蚀刻衬底（203）上的覆盖层（211）。优选地包括氮化硅的图案化器件层（206）嵌入在牺牲材料（205,209）中，优选地包括多晶硅，并且设置在耐蚀刻衬底（203）和覆盖层（211）之间。进入沟槽或孔（219）形成为覆盖层（211），并且牺牲材料（205,209）通过通路沟槽（219）被选择性蚀刻，使得器件层（206）的部分从牺牲层材料（205,209）。蚀刻剂优选包含惰性气体氟化物NgF2x（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。在蚀刻该牺牲材料（205,209）之后，密封接入沟槽（219）以将该器件层（206）的封装（241）释放部分封装在耐蚀刻衬底（203）和覆盖层（211）之间。本发明对于制造具有多个释放特征的MEM器件，多腔器件和器件特别有用。

2. 发明申请

WO2004021398A2 WAFER-LEVEL SEAL FOR NON-SILICON-BASED DEVICES 审中-公开
标题翻译：用于非硅基器件的晶片级封装
公开(公告)号：WO2004021398A2
公开(公告)日：2004-03-11
申请号：PCT/US2003/018103
申请日：2003-06-09
申请人： SILICON LIGHT MACHINES, INC.
发明人： MILLER, Gregory, D. , BRUNER, Mike , RAGAN, Lawrence, H. , GREEN, Gary, W.
IPC分类号： H01L
CPC分类号： B81C1/00293 , B81C2203/0136 , H03H3/08 , H03H9/02921 , H03H9/02984 , H03H9/1092
摘要： One embodiment disclosed relates to a method (100) for sealing an active area of a non-silicon-based device on a wafer. The method includes providing (104) a sacrificial material over at least the active area of the non-silicon-based device, depositing (108) a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing (112, 114) the sacrificial material with a target atmosphere. Another embodiment disclosed relates to an SAW device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, an electrical contact area (4), and a lithographically-formed structure (24) sealing at least the active area and leaving at least a portion of the electrical contact area (4) exposed.
摘要翻译：所公开的一个实施例涉及用于密封晶片上的非硅基器件的有源区的方法（100）。该方法包括在非硅基器件的至少有源区域上方提供（104）牺牲材料，在晶片上沉积（108）密封涂层，使得密封涂层覆盖牺牲材料， 114）具有目标气氛的牺牲材料。所公开的另一个实施例涉及一种在晶片级密封的SAW器件（即在晶片与晶片分离之前）。该装置包括待保护的有源区域，电接触区域（4）以及至少密封有源区域并使电接触区域（4）的至少一部分暴露的光刻成形结构（24）。 / p>

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