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1. 发明申请

WO2002082652A2 SYSTEM AND METHOD FOR MULTIPLE-PHASE CLOCK GENERATION 审中-公开
标题翻译：多相时钟生成系统与方法
公开(公告)号：WO2002082652A2
公开(公告)日：2002-10-17
申请号：PCT/US2002/011177
申请日：2002-04-09
申请人： SILICON IMAGE , KIM, Ook , LI, Hung, Sung , LEE, Inyeol , KIM, Gyudong , LEE, Yongman
发明人： KIM, Ook , LI, Hung, Sung , LEE, Inyeol , KIM, Gyudong , LEE, Yongman
IPC分类号： H03K19/00
CPC分类号： H03K23/542 , G06F1/06 , H03K5/15013 , H03L7/0891 , H03L7/0995

2. 发明申请

WO2010123753A1 STAGGERED LINE INVERSION AND POWER REDUCTION SYSTEM AND METHOD FOR LCD PANELS 审中-公开
标题翻译： STAGGERED LINE INVERSION和功率降低系统和LCD面板的方法
公开(公告)号：WO2010123753A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/031235
申请日：2010-04-15
申请人： APPLE INC. , LEE, Yongman
发明人： LEE, Yongman
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3655 , G09G2300/0426 , G09G2300/0434 , G09G2310/0224 , G09G2310/065 , G09G2320/0233 , G09G2330/021
摘要： Systems and methods are disclosed for various inversion techniques for an LCD array, such as a staggered 2-line inversion, a staggered 1-line inversion, or a staggered N-line inversion. The staggered inversion may invert 2-lines, 1-line or N-lines of an array over the duration of a frame displayed on the array. Additional systems and methods may include a high impedance power reduction technique that may be applied alone or in combination with the various inversion techniques. Specifically, electrode drivers for "idle" lines of a staggered 1-line, 2-line, or N-line inversion may be switched to a high impedance state such that the corresponding drivers for the idle lines use reduced power during the inversion of the "active" lines.
摘要翻译：公开了用于LCD阵列的各种反转技术的系统和方法，例如交错的2线反转，交错的1行反转或交错的N线反演。在阵列上显示的帧的持续时间内，交错反转可能反转阵列的2行，1行或N行。附加的系统和方法可以包括可以单独使用或与各种反转技术组合应用的高阻抗功率降低技术。具体地说，用于交错的1线，2线或N线反转的“空闲”线的电极驱动器可以被切换到高阻抗状态，使得用于空闲线的相应驱动器在反相期间使用降低的功率 “活跃”线。

3. 发明申请

WO2011119294A1 SHARED VOLTAGE DIVIDER GENERATING REFERENCE VOLTAGES FOR THE GAMMA AND COMMON ELECTRODE VOLTAGES 审中-公开
标题翻译：共享电压分压器产生伽马和常用电极电压的参考电压
公开(公告)号：WO2011119294A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/026493
申请日：2011-02-28
申请人： APPLE INC. , LEE, Yongman
发明人： LEE, Yongman
IPC分类号： G09G3/36
CPC分类号： G09G3/3655 , G09G3/3696 , G09G2320/0247 , G09G2320/0276 , G09G2330/06
摘要： A display (12) having a data voltage generation circuit (122) and a common voltage generation circuit (134) that are both coupled to a common reference voltage (GND1) is provided. By utilizing a common ground, variations between the data signals relative to the common voltage may be reduced, thereby improving voltage precision and color accuracy. In one embodiment, the data voltage generation circuit (122) may include a gamma adjustment circuit (190, 192) that utilizes a resistor string (138) having a center grounding point (140). The common voltage generation circuit (134) may share the resistor string (138) and the grounding point (140) with the gamma adjustment circuit (190, 192). Thus, data voltage signals and common voltage signals may be derived based on the same voltage reference point (140). Further, by sharing the resistor string (138), the total number of circuit components in the display (12) may be reduced, thereby reducing overall chip area and/or manufacturing costs.
摘要翻译：提供具有共同参考电压（GND1）的数据电压产生电路（122）和公共电压产生电路（134）的显示器（12）。通过利用公共地面，可以减少数据信号相对于公共电压的变化，从而提高电压精度和颜色精度。在一个实施例中，数据电压产生电路（122）可以包括利用具有中心接地点（140）的电阻串（138）的伽马调整电路（190,192）。公共电压产生电路（134）可以与伽马调整电路（190,192）共享电阻串（138）和接地点（140）。因此，可以基于相同的电压参考点（140）导出数据电压信号和公共电压信号。此外，通过共享电阻串（138），可以减少显示器（12）中的电路部件的总数，从而降低整体芯片面积和/或制造成本。

4. 发明申请

WO2011119295A1 CLOCK FEEDTHROUGH AND CROSSTALK REDUCTION METHOD 审中-公开
标题翻译：时钟提供和克服减少方法
公开(公告)号：WO2011119295A1
公开(公告)日：2011-09-29
申请号：PCT/US2011/026502
申请日：2011-02-28
申请人： APPLE INC. , LEE, Yongman
发明人： LEE, Yongman
IPC分类号： H03K4/02 , H03K17/16
CPC分类号： H03K4/02 , H03K17/163
摘要： Systems and methods of the present disclosure relates generally to techniques for controlling a gate signal applied to a transistor in an electronic component. One embodiment includes decreasing a skew rate at the rising and/or falling edges of the gate signal to reduce the effects of data signal errors. Decreasing the gate signal falling edge skew rate may decrease clock feedthrough effects of the transistor, and decreasing the gate signal rising edge skew rate may decrease crosstalk effects between more than one data paths in the electronic component. The falling edge skew rate may be manipulated by initially increasing the activating voltage of the gate signal to a higher voltage, such that the gate signal may take longer to fall. The rising edge skew rate may be manipulated by increasing a voltage later during the activating period, such that the gate signal may take longer to rise.
摘要翻译：本公开的系统和方法一般涉及用于控制施加到电子部件中的晶体管的栅极信号的技术。一个实施例包括降低门信号的上升沿和/或下降沿的偏移速率，以减少数据信号误差的影响。降低栅极信号下降沿偏移速率可能会降低晶体管的时钟馈通效应，并且降低栅极信号上升沿偏移速率可能会降低电子元件中多个数据通路之间的串扰效应。可以通过最初将栅极信号的激活电压增加到更高的电压来操纵下降沿偏移速率，使得栅极信号可能需要更长的时间来下降。可以通过在激活期间稍后增加电压来操纵上升沿偏移速率，使得栅极信号可能需要更长的时间来上升。

5. 发明申请

WO2010039331A1 DISPLAY HAVING A PLURALITY OF DRIVER INTEGRATED CIRCUITS 审中-公开
标题翻译：显示有多个驱动器集成电路
公开(公告)号：WO2010039331A1
公开(公告)日：2010-04-08
申请号：PCT/US2009/053028
申请日：2009-08-06
申请人： APPLE INC. , GETTEMY, Shawn, Robert , VIERI, Carlin, James , LEE, Yongman , YAO, Wei, H.
发明人： GETTEMY, Shawn, Robert , VIERI, Carlin, James , LEE, Yongman , YAO, Wei, H.
IPC分类号： G02F1/13 , G09G3/36
CPC分类号： G02F1/13452 , G02F1/136277 , G02F2202/103 , G09G3/3666 , G09G2300/0417 , G09G2300/0426 , G09G2320/0223
摘要： An electronic device is disclosed. In some embodiments, the electronic device includes a liquid-crystal display (LCD) and a plurality of driver integrated circuits (ICs) coupled to the LCD. The driver ICs may be disposed near non-central locations along a side of the LCD, and in some embodiments, one of the driver ICs may be a master driver IC and the other driver IC or driver ICs may be slave driver ICs.
摘要翻译：公开了一种电子设备。在一些实施例中，电子设备包括液晶显示器（LCD）和耦合到LCD的多个驱动器集成电路（IC）。驱动器IC可以布置在沿着LCD的一侧的非中心位置附近，并且在一些实施例中，驱动器IC中的一个可以是主驱动器IC，并且其它驱动器IC或驱动器IC可以是从驱动器IC。

6. 发明申请

WO2009082414A1 METHOD AND APPARATUS FOR PROVIDING HIGH SPEED, LOW EMI SWITCHING CIRCUITS 审中-公开
标题翻译：提供高速，低EMI开关电路的方法和装置
公开(公告)号：WO2009082414A1
公开(公告)日：2009-07-02
申请号：PCT/US2008/008681
申请日：2008-07-15
申请人： APPLE INC. , LEE, Yongman
发明人： LEE, Yongman
IPC分类号： G09G3/20
CPC分类号： G09G3/20 , G09G2300/0426 , G09G2330/02 , G09G2330/06 , H02M1/44 , Y10T307/74 , Y10T307/937 , Y10T307/944 , Y10T307/964
摘要： Methods and apparatus are provided for generating low EMI display driver power supply. The methods and apparatus include switching circuits that utilize two groups of parallel circuit traces, each of which is coupled to one end a switching device. The two groups of traces are configured to be interleaved with each other such that no two traces from either group are next to any other traces from the same group. When the switching device is activated, current flows through the circuit and charges an energy storage element. When the switching device is deactivated, the energy storage element discharges a portion of its energy to a second energy storage element and to the driver circuits. In another embodiment, and additional circuit trace is provided which is only connected on one end and is free floating on the other end to capture the majority of EMI remaining that was generated by the switching circuit.
摘要翻译：提供了用于产生低EMI显示驱动器电源的方法和装置。所述方法和装置包括利用两组并联电路迹线的开关电路，每组并联电路迹线与开关器件的一端耦合。两组轨迹被配置为彼此交错，使得来自任一组的任何两条迹线都不与来自相同组的任何其它迹线相邻。当开关器件被激活时，电流流过电路并对能量存储元件充电。当切换装置被去激活时，能量存储元件将其能量的一部分放电到第二能量存储元件和驱动器电路。在另一个实施例中，并且提供附加电路迹线，其仅在一端连接并且在另一端自由浮动以捕获由开关电路产生的大部分EMI。

7. 发明申请

WO2010036297A1 DISPLAY WITH REDUCED PARASITIC EFFECTS 审中-公开
标题翻译：显示与减少的PARASITIC效应
公开(公告)号：WO2010036297A1
公开(公告)日：2010-04-01
申请号：PCT/US2009/004541
申请日：2009-08-07
申请人： APPLE INC. , LEE, Yongman
发明人： LEE, Yongman
IPC分类号： G09G3/36 , G02F1/13
CPC分类号： G09G3/3655 , G02F2001/133328 , G02F2001/133331 , G02F2201/46 , G09G2300/0426 , H05K1/0237 , H05K1/162 , H05K1/189 , H05K2201/0792 , H05K2201/10136
摘要： Visual artifacts in a display are reduced by moving, to the extent possible, display driver components to the display surface itself, thereby shortening conductor distances and reducing the parasitic effects caused by parasitic resistance of the conductors between the display power supply and the display, and between the stabilizing capacitors (307, 407) and the display. To avoid interference with the device housing, low-profile driver components, including either or both of stabilizing capacitors and power supply terminals (306), can be provided and bonded to the surface of the display side of the outer layer of the display. Alternatively, the stabilizing capacitors can be formed on the display side in the same way that, e.g., in an LCD display, the transparent electrodes for controlling the liquid crystals are formed.
摘要翻译：显示器中的视觉赝像通过在可能的范围内移动到显示表面本身来减少，由此缩短导体距离并减少由于显示电源和显示器之间的导体的寄生电阻引起的寄生效应，以及在稳定电容器（307,407）和显示器之间。为了避免与设备外壳的干扰，可以提供包括稳定电容器和电源端子（306）中的一个或两者的低调驱动器部件并将其结合到显示器的外层的显示侧的表面。或者，可以以与例如LCD显示器相同的方式在显示器侧形成稳定电容器，形成用于控制液晶的透明电极。

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