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    • 1. 发明申请
    • SOURCE CONTROLLED SRAM
    • 源控制SRAM
    • WO2009138739A3
    • 2010-01-28
    • PCT/GB2009001194
    • 2009-05-13
    • SILICON BASIS LTDBEAT ROBERT
    • BEAT ROBERT
    • H01L27/11G11C11/412H01L21/8244H01L27/02H03K19/177
    • H01L27/1104G11C11/412H01L27/0207H01L27/11
    • The present invention provides a CMOS SRAM cell comprising two cross-coupled inverters each comprising a pmos and an nmos transistor, a first signal line connected to the sources of each of the nmos transistors, a second signal line, parallel to the first signal line, and connected to the source of one of said pmos transistors, and a third signal line connected to the source of the other of said pmos transistors, wherein the third signal line is orthogonally connected to the first and second signal lines. The present invention also provides a CMOS SRAM cell comprising two cross-coupled inverters, a pair of bitlines for writing data to the cell, and at least one further bitline for reading data from the cell.
    • 本发明提供了一种CMOS SRAM单元,包括两个交叉耦合的反相器,每个包括一个pmos和一个nmos晶体管,连接到每个nmos晶体管的源极的第一信号线,与第一信号线平行的第二信号线, 并且连接到所述pmos晶体管之一的源极,以及连接到所述pmos晶体管中另一个的源极的第三信号线,其中所述第三信号线正交地连接到所述第一和第二信号线。 本发明还提供一种CMOS SRAM单元,其包括两个交叉耦合的反相器,用于向该单元写入数据的一对位线以及用于从该单元读取数据的至少一个另外的位线。
    • 2. 发明申请
    • DECODER CIRCUIT
    • 解码器电路
    • WO0152265A2
    • 2001-07-19
    • PCT/GB0100116
    • 2001-01-12
    • ELEMENT 14 INCBEAT ROBERT
    • BEAT ROBERT
    • G11C8/10G11C11/418G11C11/00
    • G11C11/418G11C8/10
    • A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.
    • 一种解码电路,用于根据多条输入线的状态选择多条输出线中的一条输出线,该电路包括:第一解码装置,包括:第一解码节点; 第一预充电电路,用于将第一解码节点充电到充电电位; 第一放电电路,其包括多个切换装置,每个切换装置都可以根据各条输入线的状态进行操作,以将第一解码节点耦合到放电电位; 以及第一选择电路,其耦合到所述输出线中的相应一者,并且可响应于第一启用信号而操作以在所述第一解码节点未放电的情况下选择所述输出线; 以及第二解码装置,包括:第二解码节点; 第二预充电电路,用于将第二解码节点充电至充电电位; 第二放电电路,其包括多个开关装置,每个开关装置都可以根据各个输入线的状态进行操作,以将第二解码节点耦合到放电电位; 以及第二选择电路,其耦合到所述输出线中的相应输出线并且可响应于第二使能信号而操作以在所述第二放电节点未放电的情况下选择所述输出线; 其中所述第一使能信号是从所述第二解码节点的电位导出的。