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    • 8. 发明申请
    • SEMICONDUCTOR DEVICE, ELECTRONIC APPLIANCE USING SEMICONDUCTOR DEVICE, AND DOCUMENT USING SEMICONDUCTOR DEVICE
    • 半导体器件,使用半导体器件的电子器件和使用半导体器件的文件
    • WO2010074010A1
    • 2010-07-01
    • PCT/JP2009/071197
    • 2009-12-15
    • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.ISHII, MasatoATSUMI, Tomoaki
    • ISHII, MasatoATSUMI, Tomoaki
    • G06K19/07H04B1/59H04B5/02
    • G06K19/0723G06K19/0701H01L28/10
    • A semiconductor device capable of wireless communication which has low power consumption in a step for decoding an encoded signal to obtain data is provided. The semiconductor device includes an antenna configured to convert received carrier waves into an AC signal, a rectifier circuit configured to rectify the AC signal into a DC voltage, a demodulation circuit configured to demodulate the AC signal into an encoded signal, an oscillator circuit configured to generate a clock signal having a certain frequency by supply of the DC voltage, a synchronizing circuit configured to generate a synchronized encoded signal by synchronizing the encoded signal obtained by demodulating the AC signal with the clock signal, a decoder circuit configured to decode the synchronized encoded signal into a decoded signal, and a register configured to store the decoded signal as a clock (referred to as a digital signal).
    • 提供了一种能够在用于解码编码信号以获得数据的步骤中具有低功耗的无线通信的半导体器件。 该半导体装置包括将接收的载波转换为交流信号的天线,被配置为将交流信号整流为直流电压的整流电路,被配置为将该交流信号解调为编码信号的解调电路, 通过提供DC电压产生具有一定频率的时钟信号;同步电路,被配置为通过将通过解调AC信号获得的编码信号与时钟信号同步来生成同步编码信号;解码器电路,被配置为对同步编码的 信号转换为解码信号,以及配置为将解码信号存储为时钟(称为数字信号)的寄存器。
    • 9. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    • 制造半导体器件的方法
    • WO2010035848A1
    • 2010-04-01
    • PCT/JP2009/066841
    • 2009-09-17
    • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.ATSUMI, Tomoaki
    • ATSUMI, Tomoaki
    • H01L21/82G06F17/50H01L21/822H01L27/04
    • H03K23/52Y10T29/41
    • To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an inputted signal has a lower frequency in a following stage. Thus, placement is performed preferentially from the basic cell corresponding to the frequency-division circuit into which a signal having a higher frequency is inputted, and then wiring connection is performed. In other words, the layout of a plurality of basic cells corresponding to a multistage frequency-division circuit is performed so that, as compared to a wiring into which a signal having a lower frequency is inputted, a wiring into which a signal having a higher frequency is inputted has a shorter wiring length and has less intersection with other wirings, so that parasitic capacitance and parasitic resistance of the wiring are reduced.
    • 为了减少多级分频电路中的分频电路,特别是在多级分频电路中的电流消耗,输入信号在前级具有较高的频率,并且输入信号在 后续阶段 因此,优选地从对应于输入了具有较高频率的信号的分频电路的基本单元进行布置,然后进行布线连接。 换句话说,执行与多级分频电路相对应的多个基本单元的布局,使得与输入具有较低频率的信号的布线相比,具有较高频率的信号的布线 频率输入具有较短的布线长度,并且与其它布线的交点较少,因此布线的寄生电容和寄生电阻降低。
    • 10. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • WO2006038710A1
    • 2006-04-13
    • PCT/JP2005/018728
    • 2005-10-05
    • SEMICONDUCTOR ENERGY LABORATORY CO., LTD.ATSUMI, Tomoaki
    • ATSUMI, Tomoaki
    • H04L27/06G06K19/07G06K17/00
    • H04L7/0331G06K19/0723
    • The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.
    • 本发明提供一种从载体产生具有固定脉冲宽度的时钟信号的半导体器件。 本发明还提供一种半导体器件,其中可以使用具有固定脉冲宽度的时钟信号从载波精确地获得数据。 此外,本发明提供一种与PLL电路相比具有更简单的电路配置和更小规模的半导体器件,并且消耗更少的功率。 根据本发明,通过对包含100%调制的载波进行分频而获得的信号不被用作时钟信号,并且使用校正电路来产生使用解调信号的时钟信号和通过将包含100% 调制。 根据具有这种结构的本发明,可以产生具有固定脉冲宽度的时钟信号。