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1. 发明申请

WO2011075594A1 NON-VOLATILE MEMORY WITH MULTI-GEAR CONTROL USING ON-CHIP FOLDING OF DATA 审中-公开
标题翻译：使用片上数据折叠的多种控制的非易失性存储器
公开(公告)号：WO2011075594A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060844
申请日：2010-12-16
申请人： SANDISK CORPORATION , HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
发明人： HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

2. 发明申请

WO2011075597A1 DATA TRANSFER FLOWS FOR ON-CHIP FOLDING 审中-公开
标题翻译：数据传输流程用于片上折叠
公开(公告)号：WO2011075597A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060855
申请日：2010-12-16
申请人： SANDISK CORPORATION , HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
发明人： HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
IPC分类号： G11C11/56 , G11C16/10 , G06F12/02
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7203 , G11C7/1042 , G11C16/10 , G11C2211/5641 , G11C2211/5643
摘要： A memory system and methods of its operation are presented. The memory system includes a volatile buffer memory and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. When writing data to the non-volatile memory, the data is received from a host, stored in the buffer memory, transferred from the buffer memory to into read/write registers of the non-volatile memory circuit, and then written from the read/write registers to the first section of the non-volatile memory circuit using a binary write operation. Portions of the data and then subsequently folded from the first section of the non-volatile memory to the second section of the non-volatile memory, where a folding operation includes reading the portions of the data from multiple locations in the first section into the read/write registers and performing a multi-state programming operation of the potions of the data from the read/write registers into a location the second section of the non-volatile memory. The multi-state programming operations include a first phase and a second phase and one or more of the binary write operations are performed between the phases of the multi-state programming operations.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括易失性缓冲存储器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分，以及第二部分，状态格式。当将数据写入非易失性存储器时，将数据从存储在缓冲存储器中的主机接收，从缓冲存储器传送到非易失性存储器电路的读/写寄存器，然后从读/ 使用二进制写操作将寄存器写入非易失性存储器电路的第一部分。然后将数据的部分随后从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括将第一部分中的多个位置的数据的部分读入读取 /写入寄存器，并且将数据从读/写寄存器执行到多状态编程操作到非易失性存储器的第二部分的位置。多状态编程操作包括第一阶段和第二阶段，并且在多状态编程操作的阶段之间执行二进制写入操作中的一个或多个。

3. 发明申请

WO2011056482A1 NON-VOLATILE MEMORY AND METHOD WITH POST-WRITE READ AND ADAPTIVE RE-WRITE TO MANAGE ERRORS 审中-公开
标题翻译：非易失性存储器和具有后置读取和自适应再写入管理错误的方法
公开(公告)号：WO2011056482A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/053805
申请日：2010-10-22
申请人： SANDISK CORPORATION , DUSIJA, Gautam Ashok , CHEN, Jian , AVILA, Chris , HUANG, Jianmin , GAVENS, Lee M.
发明人： DUSIJA, Gautam Ashok , CHEN, Jian , AVILA, Chris , HUANG, Jianmin , GAVENS, Lee M.
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5621 , G11C16/10 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。在将第一部分复制到第二部分之前，输入数据被写入并分级。错误管理提供检查复制数据的质量是否存在过多的错误位。在第二部分中的不同位置重复复印和检查，直到满足预定质量或者数量或重复超过预定限度。当存储器是新的，几乎没有或没有错误时，错误管理不开始，但是在内存已经老化到由其经历的擦除/程序循环的数量确定的预定量之后开始。

4. 发明申请

WO2012151131A1 NON-VOLATILE MEMORY AND METHOD HAVING EFFICIENT ON-CHIP BLOCK-COPYING WITH CONTROLLED ERROR RATE 审中-公开
标题翻译：非易失性存储器和具有控制误差率的有效片上复制的方法
公开(公告)号：WO2012151131A1
公开(公告)日：2012-11-08
申请号：PCT/US2012/035637
申请日：2012-04-27
申请人： SANDISK TECHNOLOGIES INC. , AVILA, Chris Nga Yee , HUANG, Jianmin , GAVENS, Lee M. , ALROD, Idan
发明人： AVILA, Chris Nga Yee , HUANG, Jianmin , GAVENS, Lee M. , ALROD, Idan
IPC分类号： G11C16/28 , G11C29/50
CPC分类号： G11C16/28 , G11C29/50004 , G11C2211/5634 , G11C2211/5641
摘要： A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read reference point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read reference points so that the data is read within an error budget. Once the optimal read reference point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.
摘要翻译：具有作为用于高密度存储的MLC块的写高速缓存的SLC块的非易失性存储器芯片需要将SLC块复制或折叠到MLC块中。为了避免在控制器芯片进行ECC检查的整个SLC块的页面中耗费时间的切换，仅检查小样本。通过尝试不同的读取参考点来动态地确定用于读取SLC块样本中的存储单元的最佳读取参考点，以便在误差预算内读取数据。一旦确定了最佳读取参考点，它就被用于读取整个SLC块而无需进一步的错误检查。然后可以将SLC块复制（盲目折叠）到MLC块，其置信度在错误预算之内。

5. 发明申请

WO2011056483A1 NON-VOLATILE MEMORY AND METHOD WITH ACCELERATED POST-WRITE READ TO MANAGE ERRORS 审中-公开
标题翻译：非易失性存储器和加速后置写入的方法读取管理错误
公开(公告)号：WO2011056483A1
公开(公告)日：2011-05-12
申请号：PCT/US2010/053813
申请日：2010-10-22
申请人： SANDISK CORPORATION , CHEN, Jian , GAVENS, Lee M.
发明人： CHEN, Jian , GAVENS, Lee M.
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/3418 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5641
摘要： Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group.
摘要翻译：非易失性存储器中的数据错误不可避免地随着使用而增加，并且每个单元存储更高密度的位。存储器被配置为具有以较小误差但是较低密度存储器操作的第一部分，以及以较高密度但较不牢固的存储器操作的第二部分。错误管理在复制到第二部分后提供读取和检查副本。如果副本具有过多的错误位，则在第二或第一部分的不同位置重复该复制。通过只读取样本来读取和检查副本。从具有其自己的ECC的副本的子集中选择该样本，并且估计该样本表示其正在采样的副本中的最差错误率。一个实施例具有取自组中的每个多位存储器单元的一位的样本。

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