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1. 发明申请

WO2011008356A3 TECHNIQUES FOR ADJUSTING CLOCK SIGNALS TO COMPENSATE FOR NOISE 审中-公开
标题翻译：调整时钟信号以补偿噪声的技术
公开(公告)号：WO2011008356A3
公开(公告)日：2011-03-17
申请号：PCT/US2010036792
申请日：2010-05-31
申请人： RAMBUS INC , ZERBE JARED , BATRA PRADEEP , LEIBOWITZ BRIAN
发明人： ZERBE JARED , BATRA PRADEEP , LEIBOWITZ BRIAN
IPC分类号： H03K19/0175 , H03K5/1252 , H04L25/02
CPC分类号： H04L25/0264 , G06F1/10 , H03K5/1252
摘要： A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
摘要翻译：第一集成电路（IC）具有可调延迟电路和第一接口电路。第一时钟信号被提供给可调延迟电路以产生提供给第一接口电路的延迟时钟信号。第二IC具有电源电压感测电路和与第一IC传输数据的第二接口电路。电源电压感测电路向第一IC提供噪声信号，其指示第二IC的电源电压中的噪声。可调延迟电路基于噪声信号来调整延迟时钟信号的延迟。在其他实施例中，通过使IC间的高频抖动相同，边缘彩色时钟信号减少了集成电路（IC）之间数据传输中高频抖动的影响。在其他实施例中，电源电压被用于在多个IC上产生时钟信号。

2. 发明申请

WO2013081572A3 METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 审中-公开
标题翻译：减少时钟抖动的方法和电路
公开(公告)号：WO2013081572A3
公开(公告)日：2013-08-08
申请号：PCT/US2011054615
申请日：2011-10-03
申请人： RAMBUS INC , ZERBE JARED , STONE TEVA , REN JIHONG
发明人： ZERBE JARED , STONE TEVA , REN JIHONG
IPC分类号： H03K5/1252
CPC分类号： H04L7/02 , H03K5/1252 , H03L7/00
摘要： A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
摘要翻译：通信系统包括时钟转发路径中的连续时间线性均衡器。可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

3. 发明申请

WO2011041060A3 METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE IN PROGRAMMABLE DELAY LINES 审中-公开
标题翻译：用于降低可编程延迟线中的供应和终端噪声的方法和系统
公开(公告)号：WO2011041060A3
公开(公告)日：2011-07-14
申请号：PCT/US2010047282
申请日：2010-08-31
申请人： RAMBUS INC , SATARZADEH PATRICK , ZERBE JARED , DALY BARRY
发明人： SATARZADEH PATRICK , ZERBE JARED , DALY BARRY
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H03H11/265 , H03K5/131
摘要： Described are integrated-circuit delay lines that include regulated and unregulated delay elements connected in series. The regulated delay elements exhibit relatively long delays that are stable over process, voltage, and temperature. The unregulated delay elements exhibit relatively short delays with fine adjustment granularity. A multiplexer selects various numbers of the delay elements to provide a range of delay settings. The multiplexer includes a number of smaller multiplexers cascaded to minimize the lead-in delay of the delay element. The delay elements and multiplexer can be single-ended or complementary.
摘要翻译：描述了集成电路延迟线，其包括串联连接的调节和未调节的延迟元件。调节的延迟元件表现出相对较长的延迟，其在工艺，电压和温度上稳定。未调节的延迟元件具有相对较短的延迟和精细的调整粒度。多路复用器选择各种数量的延迟元件来提供一定范围的延迟设置。多路复用器包括多个级联的小型多路复用器，以使延迟元件的导入延迟最小化。延迟元件和多路复用器可以是单端或互补的。

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