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1. 发明申请

WO2005089407A2 DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 审中-公开
标题翻译：用于通信信道的跟踪跟踪反馈
公开(公告)号：WO2005089407A2
公开(公告)日：2005-09-29
申请号：PCT/US2005/008830
申请日：2005-03-16
申请人： RAMBUS, INC. , BEST, Scott, C. , ABHYANKAR, Abhijit, M. , CHANG, Kun-Yung , LAMBRECHT, Frank
发明人： BEST, Scott, C. , ABHYANKAR, Abhijit, M. , CHANG, Kun-Yung , LAMBRECHT, Frank
IPC分类号： G06F1/04 , H04L7/00 , H04L7/10 , H04L25/14
CPC分类号： G06F1/08 , G06F1/12 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , H04L7/0004 , H04L7/0008 , H04L7/0033 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/14
摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.
摘要翻译：通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。通信链路耦合第一和第二组件。校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要响应监控功能。

2. 发明申请

WO2017023508A1 HIGH PERFORMANCE, HIGH CAPACITY MEMORY MODULES AND SYSTEMS 审中-公开
标题翻译：高性能，高容量存储器模块和系统
公开(公告)号：WO2017023508A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/042356
申请日：2016-07-14
申请人： RAMBUS INC.
发明人： RAJAN, Suresh , ABHYANKAR, Abhijit, M. , KOLLIPARA, Ravindranath , SECKER, David, A.
IPC分类号： G06F3/00
CPC分类号： G06F13/1678
摘要： Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
摘要翻译：描述的是包含地址缓冲器组件和数据缓冲器组件的内存模块，这些组件一起支持宽数据和窄数据模式。地址缓冲器组件管理存储器控制器和两组存储器组件之间的通信。在宽数据模式下，地址缓冲器启用每个集合中的存储器组件，并指示数据缓冲器组件通过组合来自两个集合的数据到每个存储器访问来传送全宽读和写数据。在窄数据模式下，地址缓冲器仅在两组之一中启用存储器组件，并指示数据缓冲器组件对每个存储器访问具有一组半帧读写数据。

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