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1. 发明申请

WO2010077776A1 SELF-TUNING OF SIGNAL PATH DELAY IN CIRCUIT EMPLOYING MULTIPLE VOLTAGE DOMAINS 审中-公开
标题翻译：在采用多个电压域的电路中进行信号路径延迟的自调节
公开(公告)号：WO2010077776A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/067657
申请日：2009-12-11
申请人： QUALCOMM Incorporated , CHAI, Chiaming , LILES, Stephen Edward
发明人： CHAI, Chiaming , LILES, Stephen Edward
IPC分类号： G11C7/08 , G11C11/413 , G11C11/417 , G11C11/419 , G11C7/22
CPC分类号： G11C7/08 , G11C7/22 , G11C7/222 , G11C11/413 , G11C11/417 , G11C11/419
摘要： Circuits and methods provided in multiple voltage domains that include self-tuning or timing of a signal path are disclosed. A plurality of paths is provided in the circuit. Each path traverses a portion of the multiple voltage domains, which may include any number or combination of the multiple voltage domains. Each of the paths has a delay responsive to at least one of the plurality of voltage domains. A delay circuit is provided and configured to generate a delay output related to the delay in the plurality of paths. In this manner, the delay output of the delay circuit is self-tuned or adjusted according to the delay in the plurality of paths. This self-tuning may be particularly suited to control the delay of a first signal path relative to a second signal path wherein the delay in the paths can vary with respect to each other during operation.
摘要翻译：公开了包括信号路径的自整定或定时在多个电压域中提供的电路和方法。在电路中提供多个路径。每个路径遍及多个电压域的一部分，其可以包括多个电压域的任何数量或组合。每个路径具有响应于多个电压域中的至少一个的延迟。延迟电路被提供并被配置为产生与多个路径中的延迟相关的延迟输出。以这种方式，延迟电路的延迟输出根据多个路径中的延迟进行自调谐或调整。该自整定可以特别适合于控制相对于第二信号路径的第一信号路径的延迟，其中路径中的延迟在操作期间可以相对于彼此而变化。

2. 发明申请

WO2011127023A1 CIRCUITS, SYSTEMS, AND METHODS FOR DYNAMIC VOLTAGE LEVEL SHIFTING 审中-公开
标题翻译：用于动态电压水平移动的电路，系统和方法
公开(公告)号：WO2011127023A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/031198
申请日：2011-04-05
申请人： QUALCOMM INCORPORATED , LILES, Stephen Edward , CHAI, Chiaming , MAMILETI, Lakshmikant
发明人： LILES, Stephen Edward , CHAI, Chiaming , MAMILETI, Lakshmikant
IPC分类号： H03K3/356 , G11C11/419
CPC分类号： H03K3/356182 , H03K3/356113
摘要： Dynamic voltage level shifting circuits, systems and methods are disclosed. A level shifting circuit comprises an input for accepting a first discrete voltage level to be shifted, a level shifting portion coupled to the input and to a second discrete voltage level, an enable portion having an enable input and coupled to the level shifting portion and an output. The level shifting circuit is configured to translate the data input at the first discrete voltage level into a second discrete voltage level. The enable portion is configured to selectively provide either the second discrete voltage level to the output or decouple at least a portion of the level shifting portion from the output based on the enable input.
摘要翻译：公开了动态电压电平移位电路，系统和方法。电平移位电路包括用于接受要移位的第一离散电压电平的输入端，耦合到输入端和第二离散电压电平的电平移位部分，具有使能输入并耦合到电平转换部分的使能部分和输出。电平移位电路被配置为将在第一离散电压电平处的数据输入转换成第二离散电压电平。使能部分被配置为基于使能输入，选择性地将输出的第二离散电压电平或电平移位部分的至少一部分从输出分离。

3. 发明申请

WO2010085560A1 LOW LEAKAGE HIGH PERFORMANCE STATIC RANDOM ACCESS MEMORY CELL USING DUAL-TECHNOLOGY TRANSISTORS 审中-公开
标题翻译：低泄漏高性能静态随机访问存储器单元使用双技术晶体管
公开(公告)号：WO2010085560A1
公开(公告)日：2010-07-29
申请号：PCT/US2010/021652
申请日：2010-01-21
申请人： QUALCOMM INCORPORATED , GARG, Manish , CHAI, Chiaming , PHAN, Michael, Thai Thanh
发明人： GARG, Manish , CHAI, Chiaming , PHAN, Michael, Thai Thanh
IPC分类号： G11C8/08 , G11C11/408 , G11C11/419
CPC分类号： G11C11/419 , G11C8/08
摘要： A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
摘要翻译：存储单元包括存储元件，耦合到存储元件的写入电路和耦合到存储元件的读取电路。使用较厚的功能栅极氧化物制造存储元件的至少一部分和写入电路的至少一部分，并且使用更薄的功能栅极氧化物制造读取电路的至少一部分。

4. 发明申请

WO2009003120A1 LOGIC STATE CATCHING CIRCUITS 审中-公开
标题翻译：逻辑状态捕捉电路
公开(公告)号：WO2009003120A1
公开(公告)日：2008-12-31
申请号：PCT/US2008/068395
申请日：2008-06-26
申请人： QUALCOMM INCORPORATED , GE, Shaoping , CHAI, Chiaming , FISCHER, Jeffery Herbert
发明人： GE, Shaoping , CHAI, Chiaming , FISCHER, Jeffery Herbert
IPC分类号： H03K5/1534 , G01R29/027
CPC分类号： H03K5/1534 , H03K19/19
摘要： A number of logic state catching circuits (200) are described which use a logic circuit (204) with a first input (210), a second input, (232) and an output. The logic circuit (204) is configured to respond to a change in state of a data value coupled to the first input (210) causing a representative value of the data „ value to be generated on the output(212). The second input (232) receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element (206) is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input (232). A reset element (208) is configured to respond to a change in state of a clock input (230)by resetting the latching element. (206)
摘要翻译：描述了使用具有第一输入（210），第二输入（232）和输出的逻辑电路（204）的多个逻辑状态捕捉电路（200）。逻辑电路（204）被配置为响应耦合到第一输入（210）的数据值的状态变化，导致在输出（212）上产生数据“值的代表值”，第二输入 232）接收数据值的锁存版本，以在数据值已经返回到其原始状态之后将输出的代表值保持在该状态。锁存元件（206）被配置为通过锁存来响应数据值的状态改变数据值并将锁存的数据值版本耦合到第二输入端（232），复位元件（208）被配置为通过复位锁存元件来响应时钟输入（230）的状态改变（ 206）

5. 发明申请

WO2011081951A1 ADAPTIVE CLOCK GENERATORS, SYSTEMS, AND METHODS 审中-公开
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：WO2011081951A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/060361
申请日：2010-12-14
申请人： QUALCOMM INCORPORATED , GARG, Manish , CHAI, Chiaming , BRIDGES, Jeffrey Todd
发明人： GARG, Manish , CHAI, Chiaming , BRIDGES, Jeffrey Todd
IPC分类号： H03K3/03 , H03K5/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

6. 发明申请

WO2008064172A2 CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：内容可寻址内存
公开(公告)号：WO2008064172A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/085129
申请日：2007-11-19
申请人： QUALCOMM Incorporated , CHAI, Chiaming , HOFF, David, Paul , MARTZLOFF, Jason, Philip , PHAN, Michael, Thaithanh , VARMA, Manju, Rathna
发明人： CHAI, Chiaming , HOFF, David, Paul , MARTZLOFF, Jason, Philip , PHAN, Michael, Thaithanh , VARMA, Manju, Rathna
IPC分类号： H01L21/8239 , H01L27/02 , H01L27/105 , G11C15/04
CPC分类号： H01L27/105 , G11C11/412 , G11C15/00 , G11C15/04 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/1052
摘要： A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.
摘要翻译：公开了内容可寻址存储器（CAM）。 CAM具有第一和第二CAM单元，其中每个相邻的CAM单元相对于其邻居旋转180°，这提供了具有整体匹配的CAM阵列单元和RAM阵列单元行高度的紧凑的物理布置。此外，交错集合方案可以应用于CAM单元，以提供比较信号的降低的路由以及降低的寄生电容。

7. 发明申请

WO2007051204A1 CIRCUIT AND METHOD FOR SUBDIVIDING A CAMRAM BANK BY CONTROLLING A VIRTUAL GROUND 审中-公开
标题翻译：通过控制虚拟地面来分散CAMRAM银行的电路和方法
公开(公告)号：WO2007051204A1
公开(公告)日：2007-05-03
申请号：PCT/US2006/060370
申请日：2006-10-30
申请人： QUALCOMM INCORPORATED , PHAN, Michael, ThaiThanh , CHAI, Chiaming , BRIDGES, Jeffrey, Todd , FISCHER, Jeffrey, Herbert
发明人： PHAN, Michael, ThaiThanh , CHAI, Chiaming , BRIDGES, Jeffrey, Todd , FISCHER, Jeffrey, Herbert
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G11C8/12 , G11C15/04
摘要： A CAM bank is functionally divided into two or more sub-banks, without replicating CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in entries comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decoded from address bits, are distributed to the switching circuits to define the CAM sub-banks.
摘要翻译： CAM组在功能上划分为两个或更多个子行，不复制CAM驱动电路，禁止该组中的所有匹配线放电电路，并且选择性地使得放电电路在包含子行的条目中使能。至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。可以从地址位解码的控制信号被分配给切换电路以定义CAM子库。

8. 发明申请

WO2011116316A3 METHOD AND APPARATUS FOR SUPPRESSING BITLINE COUPLING THROUGH MILLER CAPACITANCE TO A SENSE AMPLIFIER INTERSTITIAL NODE 审中-公开
公开(公告)号：WO2011116316A3
公开(公告)日：2011-09-22
申请号：PCT/US2011/029046
申请日：2011-03-18
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
发明人： PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
IPC分类号： G11C7/06
摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

9. 发明申请

WO2008019274A2 METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：用于减少内部可寻址存储器中的功耗的方法和装置
公开(公告)号：WO2008019274A2
公开(公告)日：2008-02-14
申请号：PCT/US2007/074999
申请日：2007-08-01
申请人： QUALCOMM INCORPORATED , CHAI, Chiaming , FISCHER, Jeffrey, Herbert , PHAN, Michael, ThaiThanh
发明人： CHAI, Chiaming , FISCHER, Jeffrey, Herbert , PHAN, Michael, ThaiThanh
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： Power consumption in a multi-level hierarchical Content Addressable Memory (CAM) circuit is reduced without adversely impacting performance. According to one embodiment of a multi-level hierarchical CAM circuit, the CAM circuit comprises a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state responsive to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilized.
摘要翻译：降低了多层分级内容可寻址存储器（CAM）电路中的功耗，而不会对性能造成不利影响。根据多级分级CAM电路的一个实施例，CAM电路包括多个下级匹配线，多个较高级别匹配线和匹配线恢复电路。低级别匹配行被配置为在预评估期间恢复到预评估状态。更高级别的匹配行被配置为在评估期间捕获一个或多个下级匹配行的各个组的评估状态，并且在预评估周期期间恢复到预评估状态。匹配线恢复电路被配置为响应于相应的使能信息来防止下级匹配线中的至少一个被恢复到预评估状态，例如，指示是否要利用匹配线搜索结果的一个或多个比特。

10. 发明申请

WO2007051205A1 HIGH SPEED CAM LOOKUP USING STORED ENCODED KEY 审中-公开
标题翻译：使用存储编码键的高速凸轮
公开(公告)号：WO2007051205A1
公开(公告)日：2007-05-03
申请号：PCT/US2006/060371
申请日：2006-10-30
申请人： QUALCOMM INCORPORATED , FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
发明人： FISCHER, Jeffrey Herbert , PHAN, Michael Thaithanh , CHAI, Chiaming , DIEFFENDERFER, James Norris
IPC分类号： G11C15/04
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译：高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。在缓存物理标记的地方，搜索关键字是物理地址。物理地址的页地址部分在被存储在TLB中之前被编码。页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。这些子页地址可以被编码并存储在微型TLB中。编码的密钥和密钥字段容忍单位软错误。

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