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1. 发明申请

WO1995008888A1 MULTIRATE SERIAL VITERBI DECODER FOR CODE DIVISION MULTIPLE ACCESS SYSTEM APPLICATIONS 审中-公开
标题翻译：用于编码部分多路访问系统应用程序的多重串行VITERBI解码器
公开(公告)号：WO1995008888A1
公开(公告)日：1995-03-30
申请号：PCT/US1994010774
申请日：1994-09-23
申请人： QUALCOMM INCORPORATED
发明人： QUALCOMM INCORPORATED , KINDRED, Daniel, Ray , BUTLER, Brian, K. , ZEHAVI, Ephraim , WOLF, Jack, Keil
IPC分类号： H04L25/02
CPC分类号： H03M13/3776 , H03M13/37 , H03M13/41 , H04B1/707 , H04B2201/70703 , H04L1/0009 , H04L1/0032 , H04L1/0046 , H04L1/0052 , H04L1/0054 , H04L1/0071 , H04L1/08 , H04L1/20 , H04L1/208 , H04L25/0262 , H04L25/03178
摘要： A Viterbi decoder (20) for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system (22). The decoder (20) simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder (20) can decode at an unknown data rate in either continuous or framed packed modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder (50) from system timing constraints. The input buffer (48) includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates. Decoded data packets for each of several predetermined data transfer rates are held in an output buffer (54) for about half of the decoding cycle, thereby permitting the system microprocessor to examine and select the appropriate decoded data packet. The decoder (50) also can be reconfigured to operate at any one of several predetermined convolutional encoding algorithms. The Viterbi decoder (20), implemented as a single monolithic integrated circuit, can be used in any and all of many different multiuser telecommunications channels.
摘要翻译：一种用于在码分多址（CDMA）移动通信系统（22）中恢复被卷积编码为码符号流的原始比特数据流的维特比解码器（20）。解码器（20）以与某些多速率声码器相关联的几个数据速率同时解码。解码器（20）可以以连续或框架打包模式中的未知数据速率进行解码。它通过以多个速率同时解码并通过为每个解码的数据分组创建一个或多个数据质量度量来实现。提供特殊的输入和输出缓冲以将解码器（50）与系统时序约束隔离开来。输入缓冲器（48）包括选择和累积逻辑，用于以较低帧数据速率将代码符号数据组织成用于重复模式或随机突发模式的分组顺序。用于数个预定数据传送速率中的每一个的解码的数据分组被保存在输出缓冲器（54）中约一半的解码周期，从而允许系统微处理器检查并选择适当的解码数据分组。解码器（50）还可以被重新配置为在几个预定的卷积编码算法中的任何一个上进行操作。实现为单个单片集成电路的维特比解码器（20）可以用于许多不同的多用户电信信道中的任何一个和全部。

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