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1. 发明申请

WO2014004706A1 QUALIFYING SOFTWARE BRANCH-TARGET HINTS WITH HARDWARE-BASED PREDICTIONS 审中-公开
标题翻译：以硬件为基础的质量评估软件分支目标
公开(公告)号：WO2014004706A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/047956
申请日：2013-06-26
申请人： QUALCOMM INCORPORATED
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , STREETT, Daren Eugene , REDDY, Vimal K.
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A processor architecture to qualify software target-branch hints with hardwarebased predictions, the processor including a branch target address cache (120) having entries (122), where an entry includes a tag field to store an instruction address, a target field to store a target address, and a state field to store a state value. Upon decoding an indirect branch instruction (302), the processor determines whether an entry in the branch target address cache has an instruction address that matches the address of the decoded indirect branch instruction (306); and if there is a match, depending upon the state value stored in the entry (310), the processor will use the stored target address as the predicted target address (312) for the decoded indirect branch instruction, or will use a software provided target address hint if available.
摘要翻译：一种处理器架构，用于基于硬件预测来限定软件目标分支提示，所述处理器包括具有条目（122）的分支目标地址高速缓存（120），其中条目包括用于存储指令地址的标签字段，存储目标地址和状态字段来存储状态值。在解码间接分支指令（302）时，处理器确定分支目标地址高速缓存中的条目是否具有与解码的间接转移指令（306）的地址相匹配的指令地址; 并且如果存在匹配，则根据存储在条目（310）中的状态值，处理器将使用存储的目标地址作为解码的间接分支指令的预测目标地址（312），或将使用提供软件的目标地址提示（如果有）。

2. 发明申请

WO2014085683A1 ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：建立分支目标指导缓存（BTIC）进入SUBRONTINE返回以减少执行管道泡沫以及相关系统，方法和计算机可读介质
公开(公告)号：WO2014085683A1
公开(公告)日：2014-06-05
申请号：PCT/US2013/072372
申请日：2013-11-27
申请人： QUALCOMM INCORPORATED
发明人： DIEFFENDERFER, James Norris , MORROW, Michael William , MCILVAINE, Michael Scott , STREETT, Daren Eugene , REDDY, Vimal K. , STEMPEL, Brian Michael
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3808 , G06F9/30054
摘要： Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.
摘要翻译：建立用于子程序的分支目标指令缓存（BTIC）条目返回以减少管道气泡，以及相关系统，方法和计算机可读介质。在一个实施例中，建立BTIC条目的方法包括检测执行流水线中的子程序调用。作为响应，在子程序返回的BTIC条目中写入与子程序调用顺序取得的至少一个指令作为分支目标指令。计算下一个指令提取地址，并将其写入BTIC条目中的下一个指令获取地址字段。以这种方式，即使第一次遇到子程序返回或从不同的呼叫位置调用子程序，BTIC可以为子程序返回提供正确的分支目标指令和下一个指令获取地址数据。

3. 发明申请

WO2014004272A1 METHODS AND APPARATUS TO EXTEND SOFTWARE BRANCH TARGET HINTS 审中-公开
标题翻译：扩展软件分支目标的方法和设备
公开(公告)号：WO2014004272A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046975
申请日：2013-06-21
申请人： QUALCOMM INCORPORATED
发明人： REDDY, Vimal K.
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844
摘要： Apparatus and techniques for predicting a storage address based on contents of a first program accessible register (PAR) specified in a first instruction, wherein the first PAR correlates with a target address specified by a second PAR in a second instruction. Information is speculatively fetched at the predicted storage address prior to execution of the second instruction. The first instruction is an advance correlating notification (ADVCN) instruction, the second instruction is an indirect branch instruction, and the information is a plurality of instructions beginning at the predicted storage address. The predicted storage address is a branch target address for the indirect branch instruction from which instructions are speculatively fetched. The prediction is based on contents of the first PAR specified in the ADVCN instruction. The contents of the first PAR correlate with a taken evaluation of the branch instruction.
摘要翻译：用于基于在第一指令中指定的第一程序可访问寄存器（PAR）的内容来预测存储地址的装置和技术，其中所述第一PAR与第二指令中由第二PAR指定的目标地址相关联。在执行第二条指令之前，在预测的存储地址推测地获取信息。第一指令是提前相关通知（ADVCN）指令，第二指令是间接分支指令，并且该信息是从预测存储地址开始的多个指令。预测的存储地址是用于间接转移指令的分支目标地址，从该指令中推测性地获取指令。该预测是基于ADVCN指令中指定的第一个PAR的内容。第一PAR的内容与分支指令的评估结果相关。

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