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1. 发明申请

WO2013049759A1 PROCESSOR HARDWARE PIPELINE CONFIGURED FOR SINGLE INSTRUCTION ADDRESS EXTRACTION AND MEMORY ACCESS OPERATION 审中-公开
标题翻译：处理器硬件管道配置为单指令地址提取和存储器访问操作
公开(公告)号：WO2013049759A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058174
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , DE, Subrato K. , MORROW, Michael William , KHAN, Moinul H. , BAPST, Mark
发明人： DE, Subrato K. , MORROW, Michael William , KHAN, Moinul H. , BAPST, Mark
IPC分类号： G06F9/30
CPC分类号： G06F9/30043
摘要： Memory access instructions, such as load and store instructions, are processed in a processor-based system. Processor hardware pipeline configurations enable efficient performance of memory access instructions, such as a pipeline configuration that enables, for a memory access operation request by a register-operand based virtual machine, computation of the memory location corresponding to a virtual-machine register by extracting a bit-field from the virtual-machine instruction and accessing (load or store) the computed memory location that represents a virtual register of the virtual-machine, in a single pass through the pipeline. Thus this processor hardware pipeline configuration enables a virtual machine register read/write operation to be performed by a single hardware processor instruction through a single pass in the processor hardware pipeline, for a register-operand based virtual machine.
摘要翻译：诸如加载和存储指令之类的存储器访问指令在基于处理器的系统中被处理。处理器硬件流水线配置能够有效地执行存储器访问指令，例如流水线配置，其能够通过基于寄存器操作数的虚拟机对存储器访问操作请求进行与虚拟机寄存器对应的存储器位置的计算，来自虚拟机指令的位字段，并且在通过管道的单次通过中访问（加载或存储）表示虚拟机的虚拟寄存器的计算的存储器位置。因此，这种处理器硬件流水线配置使得能够通过单个硬件处理器指令通过处理器硬件流水线中的单次执行对基于寄存器操作数的虚拟机执行虚拟机寄存器读/写操作。

2. 发明申请

WO2008073741A1 METHODS AND APPARATUS FOR LOW-COMPLEXITY INSTRUCTION PREFETCH SYSTEM 审中-公开
标题翻译：低复杂度指导预制系统的方法和装置
公开(公告)号：WO2008073741A1
公开(公告)日：2008-06-19
申请号：PCT/US2007/086254
申请日：2007-12-03
申请人： QUALCOMM Incorporated , MORROW, Michael William , DIEFFENDERFER, James Norris
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0862
摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X% into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
摘要翻译：当在指令高速缓存中发生错误时，使用预取技术来最小化错误率，存储器访问带宽和功率使用。当缺失发生时，预取技术之一运行。接收到在指令高速缓存中丢失的获取地址的通知。分析导致遗漏的提取地址，以确定提取地址的属性，并根据属性预取一行指令。该属性可以指示提取地址是非顺序操作的目标地址。另一个属性可以指示提取地址是非顺序操作的目标地址，并且目标地址大于高速缓存行中的X％。进一步的属性可以指示提取地址是指令高速缓存中的偶数地址。可以组合这些属性以确定是否预取。

3. 发明申请

WO2008092032A1 METHOD AND APPARATUS FOR SETTING CACHE POLICIES IN A PROCESSOR 审中-公开
标题翻译：用于在处理器中设置高速缓存的方法和装置
公开(公告)号：WO2008092032A1
公开(公告)日：2008-07-31
申请号：PCT/US2008/051953
申请日：2008-01-24
申请人： QUALCOMM Incorporated , MORROW, Michael William
发明人： MORROW, Michael William
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/121 , G06F12/0804 , G06F12/0888 , G06F12/0897 , G06F12/1027
摘要： According to the methods and apparatus taught herein, processor caching policies are determined using cache policy information associated with a target memory device accessed during a memory operation. According to one embodiment of a processor, the processor comprises at least one cache and a memory management unit. The at least one cache is configured to store information local to the processor. The memory management unit is configured to set one or more cache policies for the at least one cache. The memory management unit sets the one or more cache policies based on cache policy information associated with one or more target memory devices configured to store information used by the processor.
摘要翻译：根据本文教导的方法和装置，使用与在存储器操作期间访问的目标存储器设备相关联的高速缓存策略信息来确定处理器高速缓存策略。根据处理器的一个实施例，处理器包括至少一个高速缓存和存储器管理单元。至少一个缓存被配置为存储处理器本地的信息。存储器管理单元被配置为为至少一个高速缓存设置一个或多个高速缓存策略。存储器管理单元基于与被配置为存储由处理器使用的信息的一个或多个目标存储器设备相关联的高速缓存策略信息设置一个或多个高速缓存策略。

4. 发明申请

WO2012119148A1 MEMORY MANAGEMENT UNIT WITH PRE-FILLING CAPABILITY 审中-公开
标题翻译：具有预填充能力的内存管理单元
公开(公告)号：WO2012119148A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/027739
申请日：2012-03-05
申请人： QUALCOMM INCORPORATED , RYCHLIK, Bohuslav , SARTORIUS, Thomas Andrew , MORROW, Michael William , PALMA, Raymond P.
发明人： RYCHLIK, Bohuslav , SARTORIUS, Thomas Andrew , MORROW, Michael William , PALMA, Raymond P.
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) (206, 208) with address translation (202-204) entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices (214), or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns (216). Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译：用于存储器管理单元（MMU）的系统和方法，被配置为使用预期在将来使用的地址转换（202-204）的条目自动预填充翻译后备缓冲器（206,208），从而减少TLB未命中率并提高性能。可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。可以从外部设备（214）或基于步幅值导出预测，其中步幅值可以是预定常数或基于访问模式（216）动态地改变。预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

5. 发明申请

WO2009059100A1 A METHOD AND A SYSTEM FOR ACCELERATING PROCEDURE RETURN SEQUENCES 审中-公开
标题翻译：一种用于加速程序返回序列的方法和系统
公开(公告)号：WO2009059100A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081947
申请日：2008-10-31
申请人： QUALCOMM Incorporated , MORROW, Michael William , DIEFFENDERFER, James Norris
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/322 , G06F9/382
摘要： A method for retrieving a return address from a link stack when returning from a procedure in a pipeline processor is disclosed. The method identifies a retrieve instruction operable to retrieve a return address from a software stack. The method further identifies a branch instruction operable to branch to the return address. The method retrieves the return address from the link stack, in response to both the instruction and the branch instruction being identified and fetches instructions using the return address.
摘要翻译：公开了一种在从流水线处理器中的过程返回时从链接堆栈检索返回地址的方法。该方法识别可操作以从软件堆栈检索返回地址的检索指令。该方法进一步标识可分支到返回地址的分支指令。该方法响应于正在识别的指令和分支指令，并使用返回地址获取指令，从链接堆栈检索返回地址。

6. 发明申请

WO2009009704A1 DATA PREFETCH THROTTLE 审中-公开
标题翻译：数据预设曲线
公开(公告)号：WO2009009704A1
公开(公告)日：2009-01-15
申请号：PCT/US2008/069710
申请日：2008-07-10
申请人： QUALCOMM INCORPORATED , MORROW, Michael William , DIEFFENDERFER, James Norris
发明人： MORROW, Michael William , DIEFFENDERFER, James Norris
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A system and method taught herein control data prefetching for a data cache by tracking prefetch hits and overall hits for the data cache. Data prefetching for the data cache is disabled based on the tracking of prefetch hits and data prefetching is enabled for the data cache based on the tracking of overall hits. For example, in one or more embodiments, a cache controller is configured to track a prefetch hit rate reflecting the percentage of hits on the data cache that involve prefetched data lines and disable data prefetching if the prefetch hit rate falls below a defined threshold. The cache controller also tracks an overall hit rate reflecting the overall percentage of data cache hits (versus misses) and enables data prefetching if the overall hit rate falls below a defined threshold.
摘要翻译：本文教导的系统和方法通过跟踪数据高速缓存的预取命中和整体命中来控制数据高速缓存的数据预取。基于预取命中的跟踪，数据高速缓存的数据预取被禁用，并且基于对整体命中的跟踪，为数据高速缓存启用数据预取。例如，在一个或多个实施例中，高速缓存控制器被配置为跟踪预取命中率，其反映涉及预取数据线的数据高速缓存上的命中百分比，并且如果预取命中率低于定义的阈值则禁用数据预取。高速缓存控制器还跟踪总体命中率，反映数据高速缓存命中的总体百分比（相对于未命中），如果总命中率低于定义的阈值，则可实现数据预取。

7. 发明申请

WO2007130789A2 METHOD AND APPARATUS FOR CACHING VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：用于缓存可变长度指令的方法和装置
公开(公告)号：WO2007130789A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/066980
申请日：2007-04-19
申请人： QUALCOMM Incorporated , MORROW, Michael William
发明人： MORROW, Michael William
IPC分类号： G06F12/08 , G06F12/04
CPC分类号： G06F12/0886 , G06F9/30149 , G06F9/3816 , G06F9/382 , G06F12/0875
摘要： An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary position. In one or more embodiments, the cache controller duplicates instruction data for the post-boundary position in the supplemental memory, and multiplexes that copied data into cache data obtained from the pre-boundary position.
摘要翻译：指令高速缓存控制器使用补充存储器来存储对应于高速缓存边界位置的高速缓存指令数据的冗余副本，从而使得能够跟随越过该边界位置的指令的单次高速缓存访问检索。在一个或多个实施例中，高速缓存控制器复制补充存储器中的后边界位置的指令数据，并将该复制数据复用到从前置位置获得的高速缓存数据中。

8. 发明申请

WO2007085011A2 EFFICIENT MEMORY HIERARCHY MANAGEMENT 审中-公开
标题翻译：有效的记忆层级管理
公开(公告)号：WO2007085011A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060815
申请日：2007-01-22
申请人： QUALCOMM INCORPORATED , MORROW, Michael William , SARTORIUS, Thomas Andrew
发明人： MORROW, Michael William , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F12/0848
摘要： In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.
摘要翻译：在处理器中，在执行程序之前，存在指令和程序的某些部分可能驻留在数据高速缓存中的情况。提供硬件和软件技术，用于在指令高速缓存中未命中以提高处理器性能之后在数据高速缓存中获取指令。如果指令缓存中没有指令，则指令提取地址作为数据提取地址发送到数据缓存。如果在提供的取指地址的数据高速缓存中存在有效数据，则数据实际上是一条指令，并且数据高速缓存条目被提取并作为指令提供给处理器组合系统。指令页表中可能包含一个额外的位，以指示指令缓存中的未命中数据缓存应该检查该指令。

9. 发明申请

WO2014152064A1 METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPENDENT INSTRUCTIONS MORE EFFICIENTLY USING A CONSTANT CACHE 审中-公开
标题翻译：使用恒定缓存更有效地将文献生成数据转发给相关指令的方法和装置
公开(公告)号：WO2014152064A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/026907
申请日：2014-03-14
申请人： QUALCOMM INCORPORATED
发明人： DIEFFENDERFER, James Norris , MORROW, Michael William , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , HIGDON, Daniel S. , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , KOTHARI, Kulin Narendra
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3832 , G06F9/30032 , G06F9/3828
摘要： A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.
摘要翻译：解码将立即数移动（复制或写入）到结构化寄存器的移动即时指令时，缓存中存储恒定值（立即数或立即数）的处理器。常量值存储在缓存中的条目中。缓存中的每个条目包括一个字段，用于指示其存储的常量值是否有效，以及一个字段，用于将条目与架构化寄存器相关联。一旦常数值被存储在高速缓存中，则立即可以转发到处理器流水线，其中解码的指令可能需要常数值作为操作数。

10. 发明申请

WO2014025815A1 FUSING FLAG-PRODUCING AND FLAG-CONSUMING INSTRUCTIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：指令处理电路中的熔接生产和标签消费指令以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2014025815A1
公开(公告)日：2014-02-13
申请号：PCT/US2013/053844
申请日：2013-08-06
申请人： QUALCOMM INCORPORATED
发明人： IRWIN, Andrew S. , DIEFFENDERFER, James Norris , BROWN, Melinda J , SCHOTTMILLER, Jeffery M. , STEMPEL, Brian Michael , MCILVAINE, Michael Scott , SMITH, Rodney Wayne , MORROW, Michael William
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/30072
摘要： Fusing flag-producing and flag-consuming instructions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a flag-producing instruction indicating a first operation generating a first flag result is detected in an instruction stream by an instruction processing circuit. The instruction processing circuit also detects a flag-consuming instruction in the instruction stream indicating a second operation consuming the first flag result as an input. The instruction processing circuit generates a fused instruction indicating the first operation generating the first flag result and indicating the second operation consuming the first flag result as the input. In this manner, as a non-limiting example, the fused instruction eliminates a potential for a read-after-write hazard between the flag-producing instruction and the flag-consuming instruction.
摘要翻译：公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中对产生标记和标记消息的指令进行融合。在一个实施例中，指令处理电路在指令流中检测指示产生第一标志结果的第一操作的标志产生指令。指令处理电路还检测指示流中指示消耗第一标志结果的第二操作的指令消息指令作为输入。指令处理电路产生指示第一操作的融合指令，该第一操作产生第一标志结果并指示第二操作消耗第一标志结果作为输入。以这种方式，作为非限制性示例，融合指令消除了标志产生指令和标志消耗指令之间的写后读取危险的可能性。

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