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    • 6. 发明申请
    • HIGH LINEARITY LOW NOISE AMPLIFIER
    • 高线性低噪声放大器
    • WO2004068700A2
    • 2004-08-12
    • PCT/US2004001642
    • 2004-01-21
    • QUALCOMM INCSUN BO
    • SUN BO
    • H03F1/26H03F1/32H03F3/68H03F
    • H03F1/26H03F1/32H03F1/3223H03F3/68H03F2200/294H03F2200/372
    • A feedforward nonlinearity cancellation scheme is used to improve the linearity of a low noise amplifier (LNA). An LNA incorporates a main amplifier and an auxiliary amplifier couple to receive the same input. The outputs of the main amplifier and the auxiliary amplifier are also coupled. The auxiliary amplifier may be implemented as a very low power auxiliary amplifier having a very low linearity. The output of the auxiliary amplifier contains third-order intermodulation (IM3) products that are of similar amplitude, but opposite phase, to the IM3 products generated by the main amplifier. With the outputs of the main amplifier and the auxiliary amplifier coupled, their respective IM3 products are summed together and effectively cancel each other out. As a result, the output of the LNA contains substantially no IM3 products, and the linearity of the LNA is substantially improved.
    • 前馈非线性消除方案用于提高低噪声放大器(LNA)的线性度。 LNA集成了主放大器和辅助放大器耦合,以接收相同的输入。 主放大器和辅助放大器的输出也耦合。 辅助放大器可以被实现为具有非常低线性度的极低功率辅助放大器。 辅助放大器的输出包含与主放大器产生的IM3产品具有相似幅度但相反相位的三阶互调(IM3)产品。 随着主放大器和辅助放大器的输出耦合,它们各自的IM3产品相加在一起,并有效地相互抵消。 结果,LNA的输出基本上不含有IM3产物,并且LNA的线性度显着提高。
    • 8. 发明申请
    • DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES
    • 基于分数输入和输出相位的数字锁相环操作
    • WO2009073580A3
    • 2010-01-07
    • PCT/US2008085084
    • 2008-11-29
    • QUALCOMM INCBALLANTYNE GARY JOHNSUN BO
    • BALLANTYNE GARY JOHNSUN BO
    • H03L7/085
    • H03L7/10H03L7/085H03L7/087H03L2207/50
    • In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.
    • 在一个方面,数字PLL(DPLL)基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差(例如使用时间 - 数字转换器(TDC))来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。 在另一方面,DPLL包括合成的累加器,其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。
    • 9. 发明申请
    • DYNAMIC BIASING OF A VCO IN A PHASE-LOCKED LOOP
    • 在锁相环中的VCO的动态偏移
    • WO2009055622A2
    • 2009-04-30
    • PCT/US2008081033
    • 2008-10-23
    • QUALCOMM INCSUN BOSAHOTA GURKANWAL SINGHWU YUE
    • SUN BOSAHOTA GURKANWAL SINGHWU YUE
    • H03L7/10H03L7/08H03L7/093H03L7/107
    • H03L7/197H03J7/065H03L1/00H03L7/0802H03L7/0898H03L7/093H03L7/107H03L2207/06
    • A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.
    • 本地振荡器包括锁相环。 锁相环包括压控振荡器(VCO)和新型VCO控制电路。 VCO控制电路可以是可编程和可配置的。 在一个示例中,在VCO控制电路上接收指令以改变VCO的功率状态。 响应于在蜂窝电话中的RF信道条件(例如,信噪比确定的改变)检测到的变化,由其它电路发出指令。 作为响应,VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号,然后逐渐改变VCO偏置电流,改变VCO功率状态,然后将PLL的环路带宽缩小回原来的带宽。 当PLL保持锁定时,会发生整个PLL带宽扩大,改变VCO功率状态和缩小PLL带宽的过程。