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1. 发明申请

WO2009152105A3 DYNAMIC CALIBRATION TECHNIQUES FOR DIGITALLY CONTROLLED OSCILLATOR 审中-公开
标题翻译：数字控制振荡器的动态校准技术
公开(公告)号：WO2009152105A3
公开(公告)日：2010-04-01
申请号：PCT/US2009046642
申请日：2009-06-08
申请人： QUALCOMM INC , SUN BO , BALLANTYNE GARY JOHN , RANGARAJAN RAJAGOPALAN
发明人： SUN BO , BALLANTYNE GARY JOHN , RANGARAJAN RAJAGOPALAN
IPC分类号： H03L7/099 , H03B5/12 , H04B1/04 , H04B1/16
CPC分类号： H03L7/099 , H03L2207/06
摘要： Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.
摘要翻译：公开了用于校准数字控制振荡器（DCO）的技术。在本公开的一方面，确定用于操作DCO的初始控制代码集。识别从初始集合产生的输出频率范围。在频率范围内识别重叠的间隙或实例。对于重叠情况，从与重叠实例相对应的初始集中移除控制代码以建立修订集。对于间隙情况，将控制代码添加到初始设置中，以产生填充间隙的频率值。还公开了一种用于执行该装置的装置。

2. 发明申请

WO2009073580A3 DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES 审中-公开
标题翻译：基于分数输入和输出相位的数字锁相环操作
公开(公告)号：WO2009073580A3
公开(公告)日：2010-01-07
申请号：PCT/US2008085084
申请日：2008-11-29
申请人： QUALCOMM INC , BALLANTYNE GARY JOHN , SUN BO
发明人： BALLANTYNE GARY JOHN , SUN BO
IPC分类号： H03L7/085
CPC分类号： H03L7/10 , H03L7/085 , H03L7/087 , H03L2207/50
摘要： In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.
摘要翻译：在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。

3. 发明申请

WO2011084527A2 SIGNAL DECIMATION TECHNIQUES 审中-公开
标题翻译：信号分解技术
公开(公告)号：WO2011084527A2
公开(公告)日：2011-07-14
申请号：PCT/US2010060585
申请日：2010-12-15
申请人： QUALCOMM INC , BALLANTYNE GARY JOHN , GENG JIFENG , SUN BO
发明人： BALLANTYNE GARY JOHN , GENG JIFENG , SUN BO
IPC分类号： H03B19/00 , G06F1/08 , H03D7/16
CPC分类号： H03B19/00 , H03D7/165 , H03L7/16
摘要： Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.
摘要翻译：抽取第一周期信号以产生第二周期信号的技术。在示例性实施例中，第一周期信号由可配置的整数比除法器除以且分频器的输出被延迟可配置的分数延迟。使用例如Σ-Δ调制技术，可配置分数延迟可以是噪声形状，以在宽带宽上扩展分数延迟的量化噪声。在示例性实施例中，第一和第二周期信号可以用于从单个锁相环（PLL）输出生成通信收发器的发射（TX）和接收（RX）本地振荡器（LO）信号。

4. 发明申请

WO2010148407A3 POWER AND IMPEDANCE MEASUREMENT CIRCUITS FOR A WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译：无线通信设备的功率和阻抗测量电路
公开(公告)号：WO2010148407A3
公开(公告)日：2011-02-24
申请号：PCT/US2010039376
申请日：2010-06-21
申请人： QUALCOMM INC , SEE PUAY HOE , BALLANTYNE GARY JOHN , SAHOTA GURKANWAL SINGH , HADJICHRISTOS ARISTOTELE , CICALINI ALBERTO
发明人： SEE PUAY HOE , BALLANTYNE GARY JOHN , SAHOTA GURKANWAL SINGH , HADJICHRISTOS ARISTOTELE , CICALINI ALBERTO
IPC分类号： H04B1/04
CPC分类号： H04B1/0458 , H03H7/40
摘要： Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.
摘要翻译：所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。测量电路可以包括传感器和计算单元。传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本信号以获得第二传感器输出。计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

5. 发明申请

WO2007035738A3 BASEBAND COMPENSATION OF AN OFFSET PHASE LOCKED LOOP 审中-公开
标题翻译：偏移相位锁定环的基带补偿
公开(公告)号：WO2007035738A3
公开(公告)日：2007-05-10
申请号：PCT/US2006036490
申请日：2006-09-15
申请人： QUALCOMM INC , SEE PUAY HOE ANDREW , BALLANTYNE GARY JOHN , JAFFEE JAMES , SAHOTA GURKANWAL SINGH
发明人： SEE PUAY HOE ANDREW , BALLANTYNE GARY JOHN , JAFFEE JAMES , SAHOTA GURKANWAL SINGH
IPC分类号： H04L27/00
CPC分类号： H04L27/361 , H03C3/0966 , H03C3/0983
摘要： A phase modulator faithfully reproduces higher frequency modulation using an offset phase-locked loop (OPLL) without passing excessive noise through an increased bandwidth of the OPLL. A quadrature modulator modulates information from a baseband signal onto a passband IF signal and, after a limiter strips away amplitude variations, the OPLL reproduces the phase modulation on an RF signal. The OPLL introduces a group delay that does not vary linearly with the modulation frequency and that consequently causes distortion when uncompensated. A baseband filter filters the amplitude of the baseband signal and introduces a complementary group delay that compensates for the OPLL group delay and results in a combined group delay of the baseband filter, quadrature modulator, limiter and OPLL that remains substantially constant as modulation frequency varies. Compensating for the OPLL group delay reduces distortion and the spectral energy at offset frequencies from the carrier frequency of the RF signal.
摘要翻译：相位调制器使用偏移锁相环（OPLL）忠实地再现更高的频率调制，而不会通过OPLL的带宽增加而过多的噪声。正交调制器将信号从基带信号调制到通带IF信号上，并且在限幅器剥离幅度变化之后，OPLL再现RF信号上的相位调制。 OPLL引入了不随调制频率线性变化的群延迟，从而导致无补偿时的失真。基带滤波器对基带信号的幅度进行滤波，并引入补偿组延迟，补偿OPLL组延迟，并导致基带滤波器，正交调制器，限幅器和OPLL的组合群延迟，其随调制频率变化而保持基本恒定。补偿OPLL组延迟可以减少偏移频率下的失真和频谱能量与RF信号的载波频率。

6. 发明申请

WO2010068679A3 DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION AND ADAPTIVE DELAY MATCHING 审中-公开
标题翻译：具有两点调制和自适应延迟匹配的数字相位锁定环
公开(公告)号：WO2010068679A3
公开(公告)日：2011-02-17
申请号：PCT/US2009067354
申请日：2009-12-09
申请人： QUALCOMM INC , GENG JIFENG , BALLANTYNE GARY JOHN , FILIPOVIC DANIEL F
发明人： GENG JIFENG , BALLANTYNE GARY JOHN , FILIPOVIC DANIEL F
IPC分类号： H03C3/09
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.
摘要翻译：描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。

7. 发明申请

WO2009052457A3 METHOD AND APPARATUS FOR COMPENSATING FOR TUNING NONLINEARITY OF AN OSCILLATOR 审中-公开
标题翻译：用于校正振荡器非线性的方法和装置
公开(公告)号：WO2009052457A3
公开(公告)日：2010-05-27
申请号：PCT/US2008080405
申请日：2008-10-18
申请人： QUALCOMM INC , BALLANTYNE GARY JOHN
发明人： BALLANTYNE GARY JOHN
IPC分类号： H03C3/09 , H03C3/08
CPC分类号： H03C3/09 , H03C3/08
摘要： Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.
摘要翻译：描述了补偿振荡器的调谐功能的非线性的技术。振荡器的调谐非线性可以被建模为对振荡器的干扰输入，并且可以用相等但相反的干扰来补偿。在一种设计中，可以例如基于锁相环（PLL）中的相位误差信号和自适应确定的缩放因子来产生补偿调谐非线性的非线性校正信号。非线性校正信号可以补偿第n（例如，第二）阶调谐非线性，并且可以使用n阶（例如，平方）调制信号来导出缩放因子和非线性校正信号。可以基于非线性校正信号和可能的一个或多个其他信号来产生用于振荡器的控制信号。控制信号可以施加到振荡器以调节振荡器的振荡频率。

8. 发明申请

WO2009152106A3 DITHERING A DIGITALLY-CONTROLLED OSCILLATOR OUTPUT IN A PHASE-LOCKED LOOP 审中-公开
标题翻译：在锁相环中摆动数字控制振荡器输出
公开(公告)号：WO2009152106A3
公开(公告)日：2010-02-04
申请号：PCT/US2009046643
申请日：2009-06-08
申请人： QUALCOMM INC , BALLANTYNE GARY JOHN
发明人： BALLANTYNE GARY JOHN
IPC分类号： H03L7/099 , H03C3/09 , H03L7/085
CPC分类号： H03L7/099 , H03L2207/50 , H04B1/69
摘要： A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.
摘要翻译： PLL的数字控制振荡器（DCO）抖动，使得DCO_OUT信号具有在抖动间隔处变化的频率。在一个示例中，DCO接收输入的数字调谐字的未传输流，并接收抖动参考时钟信号REFD，并输出DCO_OUT信号，使得其频率变化以抖动间隔发生。在蜂窝电话发射机的本地振荡器中使用PLL的情况下，DCO的新颖抖动以频率扩展数字图像噪声，使得在与主本地振荡器频率偏移的特定频率处存在较少的数字图像噪声。以频率扩展数字图像噪声允许满足噪声规范，而不必增加PLL参考时钟的频率。通过避免增加参考时钟的频率以满足噪声规范，避免了功耗的增加。

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