专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2009155570A3 HARDWARE ACCELERATION FOR WWAN TECHNOLOGIES 审中-公开
标题翻译： WWAN技术的硬件加速
公开(公告)号：WO2009155570A3
公开(公告)日：2010-07-08
申请号：PCT/US2009048048
申请日：2009-06-19
申请人： QUALCOMM INC , KLINGENBRUNN THOMAS , BABBAR UPPINDER S , KUMAR VANITHA A , NAGPAL VIKAS , NARAYAN SRIRAM , JIM SAMSON , MAHESHWARI SHAILESH , LIOY MARCELLO V , KOHLENZ MATHIAS , MIR IDREAS , KHAN IRFAN A , CHHABRA GURVINDER S , TRAN JEAN-MARIE QD
发明人： KLINGENBRUNN THOMAS , BABBAR UPPINDER S , KUMAR VANITHA A , NAGPAL VIKAS , NARAYAN SRIRAM , JIM SAMSON , MAHESHWARI SHAILESH , LIOY MARCELLO V , KOHLENZ MATHIAS , MIR IDREAS , KHAN IRFAN A , CHHABRA GURVINDER S , TRAN JEAN-MARIE QD
IPC分类号： H04L1/18 , H04L9/18 , H04L12/56 , H04W12/02 , H04W36/02
CPC分类号： H04W12/02 , H04L9/065 , H04L47/10 , H04L49/90 , H04L63/0457 , H04L2209/122 , H04L2209/26 , H04L2209/80 , H04W80/02
摘要： Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.
摘要翻译：提供了无线通信的系统和方法。这些包括数据解密组件，中断处理组件，自适应聚合方法，优化的数据路径处理，缓冲池处理，数据以目的地处理的合适格式格式化的应用处理，以及其他硬件加速特征之间的密钥库处理。提供这样的系统和方法以简化逻辑设计并减轻无线网络数据处理期间的处理步骤。

2. 发明申请

WO2007115199A3 MEMORY MANAGEMENT FOR HIGH SPEED MEDIA ACCESS CONTROL 审中-公开
标题翻译：高速媒体访问控制的内存管理
公开(公告)号：WO2007115199A3
公开(公告)日：2007-12-06
申请号：PCT/US2007065678
申请日：2007-03-30
申请人： QUALCOMM INC , DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
发明人： DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/901 , H04L47/14 , H04L47/621 , H04L49/90 , H04L49/9021 , H04L49/9073 , H04W36/02 , H04W36/28 , H04W76/04 , H04W88/02 , H04W88/08
摘要： Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.
摘要翻译：本文公开的方面解决了本领域对用于高速媒体访问控制的存储器管理的需要。分组缓冲器可以存储具有第一数据结构的分组，包括分组长度，序列号和指向第二数据结构的指针。分组数据可以存储在一个或多个第二数据结构的链接列表中。发送和接收队列可以使用第一数据结构的链表或数组来形成。用于存储第一和第二数据结构的存储器位置可以保存在指示相应数据结构类型的空闲位置的列表中。公开了一种灵活的存储器架构，其中可以选择两种配置。在第一配置中，第一存储器包括用于多个流的每流参数，并且第二存储器包括分组缓冲器。在第二配置中，第一存储器包括在第二存储器中的每流参数的每流指针。数据包缓冲区位于第三个存储器中。还提出了各种其他方面。

3. 发明申请

WO2012021332A3 CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS 审中-公开
标题翻译：用于执行或促进OSCILLOSCOPE，JITTER和/或BIT错误率测试仪操作的集成电路的电路
公开(公告)号：WO2012021332A3
公开(公告)日：2012-04-12
申请号：PCT/US2011046239
申请日：2011-08-02
申请人： ALTERA CORP , LI PENG , SHIMANOUCHI MASASHI , SHUMARAYEV SERGEY , DING WEIQI , NARAYAN SRIRAM , CHOW DANIEL TUN LAI , PAN MINGDE
发明人： LI PENG , SHIMANOUCHI MASASHI , SHUMARAYEV SERGEY , DING WEIQI , NARAYAN SRIRAM , CHOW DANIEL TUN LAI , PAN MINGDE
IPC分类号： G01R31/303
CPC分类号： G01R31/31709 , G01R31/3171 , G01R31/31716 , H04L7/0337
摘要： An integrated circuit ("IC") may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate ("BER") analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.
摘要翻译：集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式