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1. 发明申请

WO03027690A9 TEST STRUCTURES FOR ESTIMATING DISHING AND EROSION EFFECTS IN COPPER DAMASCENE TECHNOLOGY 审中-公开
标题翻译：估算铜大马士革工艺腐蚀和腐蚀效果的测试结构
公开(公告)号：WO03027690A9
公开(公告)日：2003-08-07
申请号：PCT/US0230904
申请日：2002-09-27
申请人： PDF SOLUTIONS INC , CIPLICKAS DENNIS J , DECKER MARKUS , HESS CHRISTOPHER , STINE BRIAN E , WEILAND LARG
发明人： CIPLICKAS DENNIS J , DECKER MARKUS , HESS CHRISTOPHER , STINE BRIAN E , WEILAND LARG
IPC分类号： H01L21/66 , H01L21/321 , H01L23/544 , G01R31/02 , G01R31/26
CPC分类号： H01L22/34 , H01L21/3212 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable to determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).
摘要翻译：测试结构将用于腐蚀评估的第一结构（1010）与用于提取缺陷尺寸分布的第二结构（1000）组合。第一结构（1010）是可用于确定随金属高度变化的电阻值的环路结构。第二个结构是一个NEST结构（1000）。环结构（1010）的环线连接在NEST结构（1000）的两侧。

2. 发明申请

WO02073661A3 EXTRACTION METHOD OF DEFECT DENSITY AND SIZE DISTRIBUTIONS 审中-公开
标题翻译：缺陷密度和尺寸分布的提取方法
公开(公告)号：WO02073661A3
公开(公告)日：2002-11-14
申请号：PCT/US0207409
申请日：2002-03-12
申请人： PDF SOLUTIONS INC , HESS CHRISTOPHER , STASHOWER DAVID , STINE BRIAN E , WEILAND LARG H , BURCH RICHARD , CIPLICKAS DENIS J
发明人： HESS CHRISTOPHER , STASHOWER DAVID , STINE BRIAN E , WEILAND LARG H , BURCH RICHARD , CIPLICKAS DENIS J
IPC分类号： H01L21/66 , G01R31/28 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04 , G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a...301h, 302a...302h), each pair of nested serpentine lines having a shared pad between them (312a...312h).
摘要翻译：表征载体包括在基板的单层（301a ... 301h，302a ... 302h）的单个表面上具有至少一个层（300）和多对嵌套蛇形线的基板，每个一对嵌套蛇形线在它们之间具有共享垫（312a ... 312h）。

3. 发明申请

WO02073661A9 EXTRACTION METHOD OF DEFECT DENSITY AND SIZE DISTRIBUTIONS 审中-公开
标题翻译：缺陷密度和尺寸分布的提取方法
公开(公告)号：WO02073661A9
公开(公告)日：2003-01-09
申请号：PCT/US0207409
申请日：2002-03-12
申请人： PDF SOLUTIONS INC , HESS CHRISTOPHER , STASHOWER DAVID , STINE BRIAN E , WEILAND LARG H , BURCH RICHARD , CIPLICKAS DENIS J
发明人： HESS CHRISTOPHER , STASHOWER DAVID , STINE BRIAN E , WEILAND LARG H , BURCH RICHARD , CIPLICKAS DENIS J
IPC分类号： H01L21/66 , G01R31/28 , H01L21/02 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04 , G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a...301h, 302a...302h), each pair of nested serpentine lines having a shared pad between them (312a...312h).
摘要翻译：表征载体包括在基板的单层（301a ... 301h，302a ... 302h）的单个表面上具有至少一个层（300）和多对嵌套蛇形线的基板，每个一对嵌套蛇形线在它们之间具有共享垫（312a ... 312h）。

4. 发明申请

WO0137322A9 SYSTEM AND METHOD FOR PRODUCT YIELD PREDICTION USING A LOGIC CHARACTERIZATION VEHICLE 审中-公开
标题翻译：用于使用逻辑表征车辆进行产品产量预测的系统和方法
公开(公告)号：WO0137322A9
公开(公告)日：2002-09-06
申请号：PCT/US0031839
申请日：2000-11-17
申请人： PDF SOLUTIONS INC , STINE BRIAN E , HESS CHRISTOPHER , WEILAND LARG H , CIPLICKAS DENNIS J , KIBARIAN JOHN
发明人： STINE BRIAN E , HESS CHRISTOPHER , WEILAND LARG H , CIPLICKAS DENNIS J , KIBARIAN JOHN
IPC分类号： H01L21/02 , H01L21/66 , H01L21/822 , H01L23/544 , H01L27/04 , H03K19/00 , G06F17/50
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit (102) that controls the combinatorial logic circuit element. The control circuit includes an input mechanism (103) for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism (104) stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern.
摘要翻译：表征工具包括至少一个组合逻辑电路元件和控制组合逻辑电路元件的控制电路（102）。控制电路包括用于将信号的测试图案输入到组合逻辑电路元件中的输入机构（103）。输出机构（104）基于测试模式存储由组合逻辑电路元件输出的输出模式。

5. 发明申请

WO2005040961A3 METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING 审中-公开
标题翻译：用于连接测试结构或线阵列用于监控集成电路制造的方法和配置
公开(公告)号：WO2005040961A3
公开(公告)日：2007-05-31
申请号：PCT/US2004013483
申请日：2004-04-30
申请人： PDF SOLUTIONS INC , HESS CHRISTOPHER , GOLDMAN DAVID
发明人： HESS CHRISTOPHER , GOLDMAN DAVID
IPC分类号： G11C7/00 , G06F20060101
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A test chip (200) comprises at least one level having an array of regions (201). Each region (201) is capable of including at least one test structure (202). At least some of the regions (201) include respective test structures (202). The level has a plurality of driver lines (D1-D5) that provide input signals to the test structures (202). The level has a plurality of receiver lines (R1-R8) that receive output signals from the test structures (202). The level has a plurality of devices for controlling current flow. Each test structure (202) is connected to at least one of the driver lines with a first one of the devices in between. East test structure is connected to at least one of the receiver lines (R1-R8) with a second one of the devices in between, so that each of the test structures (202) can be individually addressed for testing using the driver lines (D1-D5) and receiver lines (R1-R8).
摘要翻译：测试芯片（200）包括具有区域阵列（201）的至少一个级别。每个区域（201）能够包括至少一个测试结构（202）。至少一些区域（201）包括相应的测试结构（202）。电平具有向测试结构（202）提供输入信号的多个驱动线（D1-D5）。电平具有接收来自测试结构（202）的输出信号的多个接收线（R1-R8）。该电平具有用于控制电流的多个装置。每个测试结构（202）连接到驱动器线中的至少一个，其间具有第一个设备。东测试结构与至少一个接收线（R1-R8）连接，其间的第二设备之间，使得每个测试结构（202）可以被单独寻址以使用驱动线（D1 -D5）和接收线（R1-R8）。

6. 发明申请

WO2017106575A3 INTEGRATED CIRCUIT CONTAINING DOES OF NCEM-ENABLED FILL CELLS 审中-公开
标题翻译：集成电路包含NCEM使能的充电电池
公开(公告)号：WO2017106575A3
公开(公告)日：2018-01-18
申请号：PCT/US2016067050
申请日：2016-12-15
申请人： PDF SOLUTIONS INC
发明人： LAM STEPHEN , CIPLICKAS DENNIS , BROZEK TOMASZ , CHENG JEREMY , COMENSOLI SIMONE , DE INDRANIL , DOONG KELVIN , EISENMANN HANS , FISCUS TIMOTHY , HAIGH JONATHAN , HESS CHRISTOPHER , KIBARIAN JOHN , LEE SHERRY , LIAO MARCI , LIN SHENG-CHE , MATSUHASHI HIDEKI , MICHAELS KIMON , O'SULLIVAN CONOR , RAUSCHER MARKUS , ROVNER VYACHESLAV , STROJWAS ANDRZEJ , STROJWAS MARCIN , TAYLOR CARL , VALLISHAYEE RAKESH , WEILAND LARG , YOKOYAMA NOBUHARU
IPC分类号： G06F17/50 , G01N23/00 , G01R31/26 , H01L21/66
CPC分类号： H01L22/26 , G01R31/2884 , G06F11/079 , G06F17/5045 , G06F17/5068 , G06F17/5072 , G06F17/5081 , H01L22/20 , H01L22/34 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/11803 , H01L27/11807 , H01L29/0649 , H01L29/0684 , H01L29/41725 , H01L29/45 , H01L2027/11866 , H01L2027/11875 , H01L2027/11885 , H01L2027/11887
摘要： Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments ("DOEs"), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).
摘要翻译：包含填充单元的晶圆，芯片或管芯，其结构配置为通过非接触式电气测量（“NCEM”）获取在线数据。这种NCEM使能的填充单元可以针对/暴露各种开路，短路，泄漏或过度电阻故障模式。这样的晶片，芯片或晶粒可以包括至少两个变体中的由多个NCEM使能的填充单元组成的实验设计（“DOE”），所有目标都针对相同的失效模式。

7. 发明申请

WO2004053944A3 FAST LOCALIZATION OF ELECTRICAL FAILURES ON AN INTEGRATED CIRCUIT SYSTEM AND METHOD 审中-公开
标题翻译：集成电路系统和方法电气故障的快速定位
公开(公告)号：WO2004053944A3
公开(公告)日：2004-11-04
申请号：PCT/US0339698
申请日：2003-12-11
申请人： PDF SOLUTIONS INC , CIPLICKAS DENNIS , HESS CHRISTOPHER , LEE SHERRY , WEILAND LARG H
发明人： CIPLICKAS DENNIS , HESS CHRISTOPHER , LEE SHERRY , WEILAND LARG H
IPC分类号： G01R1/04 , G01R19/00 , G01R31/26 , G01R31/28 , G01R31/307 , H01L20060101 , H01L21/20 , H01L21/44 , H01L21/66 , H01L23/544
CPC分类号： H01L22/20 , G01R31/2884 , G01R31/2894 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested employing a parallel electrical tester. The results of the electrical testing are analyzed to localize defects on the test chip.

8. 发明申请

WO2004061898A9 YIELD IMPROVEMENT 审中-公开
标题翻译： YIELD改进
公开(公告)号：WO2004061898A9
公开(公告)日：2005-09-15
申请号：PCT/US0337046
申请日：2003-11-17
申请人： PDF SOLUTIONS INC , CIPLICKAS DENNIS , DAVIS JOE , HESS CHRISTOPHER , LEE SHERRY , MALAVASI ENRICO , MOHAMMAD ABDULMOBEEN , RADOJCIC RATIBOR , STINE BRIAN , VALLISHAYEE RAKESH , ZANELLA STEFANO , DRAGONE NICOLA , GUARDIANI CARLO , QUARANTELLI MICHEL , TONELLO STEFANO , ANIRUDDHA JOSHI
发明人： CIPLICKAS DENNIS , DAVIS JOE , HESS CHRISTOPHER , LEE SHERRY , MALAVASI ENRICO , MOHAMMAD ABDULMOBEEN , RADOJCIC RATIBOR , STINE BRIAN , VALLISHAYEE RAKESH , ZANELLA STEFANO , DRAGONE NICOLA , GUARDIANI CARLO , QUARANTELLI MICHEL , TONELLO STEFANO , ANIRUDDHA JOSHI
IPC分类号： G06F17/50 , H01L20060101
CPC分类号： G06F17/5045
摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits (610). A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element (670). A yield to area ratio for the variant design element is determined (680). If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit (612).
摘要翻译：集成电路被设计成通过从设计集成电路（610）中使用的一组设计元件获得设计元件来提高制造集成电路时的产量。基于所获得的设计元素创建变体设计元素，其中所获得的设计元素的特征被修改以创建变体设计元素（670）。确定变体设计元素的产率与面积比（680）。如果变形设计元件的屈服面积比大于所获得的设计元素的屈服面积比，则保留变式设计元件以用于设计集成电路（612）。

9. 发明申请

WO2004061898A2 YIELD IMPROVEMENT 审中-公开
标题翻译： YIELD改进
公开(公告)号：WO2004061898A2
公开(公告)日：2004-07-22
申请号：PCT/US0337046
申请日：2003-11-17
申请人： PDF SOLUTIONS INC , CIPLICKAS DENNIS , DAVIS JOE , HESS CHRISTOPHER , LEE SHERRY , MALAVASI ENRICO , MOHAMMAD ABDULMOBEEN , RADOJCIC RATIBOR , STINE BRIAN , VALLISHAYEE RAKESH , ZANELLA STEFANO , DRAGONE NICOLA , GUARDIANI CARLO , QUARANTELLI MICHEL , TONELLO STEFANO , ANIRUDDHA JOSHI
发明人： CIPLICKAS DENNIS , DAVIS JOE , HESS CHRISTOPHER , LEE SHERRY , MALAVASI ENRICO , MOHAMMAD ABDULMOBEEN , RADOJCIC RATIBOR , STINE BRIAN , VALLISHAYEE RAKESH , ZANELLA STEFANO , DRAGONE NICOLA , GUARDIANI CARLO , QUARANTELLI MICHEL , TONELLO STEFANO , ANIRUDDHA JOSHI
IPC分类号： G06F17/50 , H01L20060101 , H01L
CPC分类号： G06F17/5045
摘要： An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element, where a feature of the obtained design element is modified to create the variant design element. A yield to area ratio for the variant design element is determined. If the yield to area ratio of the variant design element is greater than a yield to area ratio of the obtained design element, the variant design element is retained to be used in designing the integrated circuit
摘要翻译：集成电路设计用于通过从设计集成电路中使用的一组设计元素获得设计元素来提高制造集成电路时的产量。基于获得的设计元素创建变体设计元素，其中修改所获得的设计元素的特征以创建变体设计元素。确定变体设计元素的产出与面积比。如果变形设计元件的屈服面积比大于获得的设计元素的屈服面积比，则变形设计元素被保留用于设计集成电路

10. 发明申请

WO0137322A2 SYSTEM AND METHOD FOR PRODUCT YIELD PREDICTION USING A LOGIC CHARACTERIZATION VEHICLE 审中-公开
标题翻译：使用逻辑特征车辆进行产品预测的系统和方法
公开(公告)号：WO0137322A2
公开(公告)日：2001-05-25
申请号：PCT/US0031839
申请日：2000-11-17
申请人： PDF SOLUTIONS INC , STINE BRIAN E , HESS CHRISTOPHER , WEILAND LARG H , CIPLICKAS DENNIS J
发明人： STINE BRIAN E , HESS CHRISTOPHER , WEILAND LARG H , CIPLICKAS DENNIS J
IPC分类号： H01L21/02 , H01L21/66 , H01L21/822 , H01L23/544 , H01L27/04 , H03K19/00 , H01L
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.
摘要翻译：表征车辆包括至少一个组合逻辑电路元件和控制组合逻辑电路元件的控制电路。控制电路包括用于将信号的测试图案输入组合逻辑电路元件的输入机构。输出机构基于测试图案存储由组合逻辑电路元件输出的输出图案。环形总线将输出装置连接到输入装置以引起振荡。计数器对振荡的频率进行计数，从而测量组合逻辑电路元件的性能。

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