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1. 发明申请

WO2016126482A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING IMPLICITLY TYPED INSTRUCTIONS 审中-公开
标题翻译：矢量处理器配置为使用明确的类型说明可变长度矢量
公开(公告)号：WO2016126482A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015117
申请日：2016-01-27
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , KALASHNIKOV, Vitaly
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
摘要翻译：公开了一种计算机处理器。计算机处理器可以包括矢量单元，其包括矢量寄存器文件，其包括一个或多个寄存器以保存不同数量的元件。计算机处理器还可以包括处理逻辑，其被配置为隐含地对向量寄存器文件中的各种变化数量的元素进行键入。计算机处理器可以被实现为单片集成电路。

2. 发明申请

WO2015119955A1 DETERMINISTIC AND OPPORTUNISTIC MULTITHREADING 审中-公开
标题翻译：决策和机会多元化
公开(公告)号：WO2015119955A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014272
申请日：2015-02-03
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Muragappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3885 , G06F9/46
摘要： A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.
摘要翻译：处理设备识别具有等待发布的指令的一组软件线程。对于软件线程集合中的每个软件线程，处理设备将软件线程绑定到一组硬件上下文中的可用硬件上下文，并将绑定到软件线程的可用硬件上下文的标识符存储到下一个可用条目中有序列表。处理装置读取存储在有序列表的条目中的标识符。响应于等待发布的指令中与标识符相关联的与任何其他指令无关的指令，处理设备发出等待发布到与标识符相关联的硬件上下文的指令。

3. 发明申请

WO2016200567A1 PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT 审中-公开
标题翻译：具有高级操作系统支持的处理器
公开(公告)号：WO2016200567A1
公开(公告)日：2016-12-15
申请号：PCT/US2016/032853
申请日：2016-05-17
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan
IPC分类号： G06F9/46
CPC分类号： G06F9/30189 , G06F9/3005 , G06F9/30145 , G06F9/3851 , G06F9/462
摘要： A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.
摘要翻译：计算机处理器可以包括多个硬件线程。计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。计算机处理器可以进一步包括第二模式逻辑，以在多个硬件线程中的多于一个硬件线程同时执行第二模式中的指令。计算机处理器还可以包括在第一模式和第二模式之间切换的巫术模式逻辑。

4. 发明申请

WO2016171866A1 COMPUTER PROCESSOR WITH SEPARATE REGISTERS FOR ADDRESSING MEMORY 审中-公开
标题翻译：具有单独寄存器的计算机处理器用于寻址存储器
公开(公告)号：WO2016171866A1
公开(公告)日：2016-10-27
申请号：PCT/US2016/025279
申请日：2016-03-31
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary , GLOSSNER, C., John , HOANE, A., Joseph , HURTLEY, Paul , MURUGAPPAN, Senthilvelan , BALZOLA, Pablo
IPC分类号： G06F9/355
CPC分类号： G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
摘要： A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
摘要翻译：公开了一种具有地址寄存器文件的计算机处理器。计算机处理器可以包括存储器。计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及添加在指令中编码的位移值。

5. 发明申请

WO2016126543A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING GRAPHICS PROCESSING INSTRUCTIONS 审中-公开
标题翻译：使用图形处理指令配置可变长度矢量图的矢量处理器
公开(公告)号：WO2016126543A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015637
申请日：2016-01-29
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
摘要翻译：公开了一种计算机处理器。计算机处理器可以包括向量单元，其包括向量寄存器文件，其包括至少一个寄存器以保存不同数量的元件。计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个图形处理指令对向量寄存器堆中的变化数量的元件进行操作。计算机处理器可以被实现为单片集成电路。

6. 发明申请

WO2016126521A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING DIGITAL SIGNAL PROCESSING INSTRUCTIONS 审中-公开
标题翻译：使用数字信号处理指令配置在可变长度矢量上运行的矢量处理器
公开(公告)号：WO2016126521A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015376
申请日：2016-01-28
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan , BALZOLA, Pablo , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F15/76
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
摘要翻译：公开了一种计算机处理器。计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括一个或多个寄存器以保存不同数量的元件。计算机处理器还包括处理逻辑，其被配置为使用一个或多个数字信号处理指令对向量寄存器堆中的变化数量的元件进行操作。计算机处理器可以被实现为单片集成电路。

7. 发明申请

WO2016126516A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH ASYMMETRIC MULTI-THREADING 审中-公开
标题翻译：矢量处理器配置为使用不对称多路径的可变长度矢量
公开(公告)号：WO2016126516A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015355
申请日：2016-01-28
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan , BALZOLA, Pablo , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F9/50
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
摘要翻译：公开了一种计算机处理器。计算机处理器包括一个或多个处理器资源。计算机处理器还包括耦合到一个或多个处理器资源的多个硬件线程单元。计算机处理器可以被配置为仅通过多个硬件线程单元中的硬件线程单元的子集来同时访问一个或多个处理器资源。子集中的硬件线程的数量可以小于多个硬件线程单元中的硬件线程的总数。

8. 发明申请

WO2015119953A1 OPPORTUNITY MULTITHREADING IN A MULTITHREADED PROCESSOR WITH INSTRUCTION CHAINING CAPABILITY 审中-公开
标题翻译：具有指导性能力的多功能加工机构的机会多元化
公开(公告)号：WO2015119953A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014270
申请日：2015-02-03
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： WANG, Shenghong , GLOSSNER, C., John , NACER, Gary, J.
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3818 , G06F9/382 , G06F9/3822 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/46
摘要： A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.
摘要翻译：计算设备确定具有发布序列的多个软件线程的当前软件线程在时钟周期期间不具有等待发送到硬件线程的第一指令。计算设备识别发布序列中的一个或多个备选软件线程，其中有等待发出的指令。鉴于在等待等待的指令中确定第二指令与任何其他指令没有任何依赖关系，计算设备在计算设备的时钟周期期间从第一软件线程中选择一个或多个替代软件线程中的第二指令发行。鉴于从等待发布的每个指令提取的链接位的值，计算设备识别依赖关系。计算设备向硬件线程发出第二条指令。

9. 发明申请

WO2016126545A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING ONE OR MORE COMPLEX ARITHMETIC INSTRUCTIONS 审中-公开
标题翻译：使用一个或多个复杂算术指令配置为在可变长度向量上运行的矢量处理器
公开(公告)号：WO2016126545A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015652
申请日：2016-01-29
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , AGRAWAL, Sitij
IPC分类号： G06F15/76
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more complex arithmetic instructions. The computer processor may be implemented as a monolithic integrated circuit.
摘要翻译：公开了一种计算机处理器。计算机处理器可以包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个寄存器以保存不同数量的元件。计算机处理器还可以包括处理逻辑，其被配置为使用一个或多个复数运算指令对矢量寄存器堆中的变化数量的元件进行操作。计算机处理器可以被实现为单片集成电路。

10. 发明申请

WO2016126519A1 VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH OUT-OF-ORDER EXECUTION 审中-公开
标题翻译：配置为可变长度矢量图的操作的矢量处理器具有不合格的执行
公开(公告)号：WO2016126519A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/015365
申请日：2016-01-28
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , SENTHILVELAN, Murugappan , BALZOLA, Pablo
IPC分类号： G06F9/38 , G06F17/16
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising at least one vector register to hold a varying number of elements. The computer processor further comprises out-of-order issue logic that holds a pool of vector instructions, selects a vector instruction from the pool, and sends the vector instruction for execution. The vector instruction operates on the varying number of elements of the at least one vector register.
摘要翻译：公开了一种计算机处理器。计算机处理器包括矢量单元，其包括矢量寄存器文件，该矢量寄存器文件包括至少一个矢量寄存器以保存不同数量的元件。计算机处理器还包括保存向量指令池的无序发行逻辑，从池中选择向量指令，并发送用于执行的向量指令。向量指令对至少一个向量寄存器的元素的变化数量进行操作。

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