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1. 发明申请

WO1995010899A1 FORMING A HIGHER HIERARCHY LEVEL SIGNAL IN A SYNCHRONOUS DIGITAL COMMUNICATION SYSTEM 审中-公开
标题翻译：在同步数字通信系统中形成更高层次的信号
公开(公告)号：WO1995010899A1
公开(公告)日：1995-04-20
申请号：PCT/FI1994000461
申请日：1994-10-13
申请人： NOKIA TELECOMMUNICATIONS OY , VIITANEN, Esa , KEMPPAINEN, Vesa , SAHLMAN, Kari , OKSANEN, Toni , PATANA, Jari
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/16
CPC分类号： H04J3/1611 , H04J3/047 , H04J2203/0089
摘要： The invention relates to a method and a circuit arrangement for forming a higher hierarchy level signal in a synchronous digital communication system. According to the method, (a) several lower hierarchy level signals are formed by means of separate circuits (22), and (b) a higher hierarchy level signal is formed by combining several lower level signals into one higher level signal. To form a higher hierarchy level signal as simply as possible, said separate circuits (22) are chained by means of a common bus (51) into a chain where said bus connects the separate circuits (22), in each circuit (22) the data of the channels to be formed by that circuit is added to the time slots corresponding to these channels in a higher hierarchy level frame, to the data of channels possibly added already in the other circuits of the chain, and the formed signal is connected forward from the circuit at the end of the chain.
摘要翻译：本发明涉及一种用于在同步数字通信系统中形成较高层级信号的方法和电路装置。根据该方法，（a）通过分离的电路（22）形成若干较低级别的信号，（b）通过将多个较低电平信号组合成一个较高电平的信号形成较高层次的电平信号。为了尽可能简单地形成更高级别的信号，所述分离电路（22）通过公共总线（51）链接成链，其中所述总线连接每个电路（22）中的分离电路（22），将要由该电路形成的信道的数据添加到与较高级别的帧中的这些信道相对应的时隙中，可能已经添加到链的其他电路中的信道的数据，并且形成的信号被正向连接从链路末端的电路。

2. 发明申请

WO1993025030A1 METHOD FOR DISASSEMBLING AND ASSEMBLING FRAME STRUCTURES CONTAINING POINTERS 审中-公开
标题翻译：拆卸和组装包含点的框架结构的方法
公开(公告)号：WO1993025030A1
公开(公告)日：1993-12-09
申请号：PCT/FI1993000237
申请日：1993-06-01
申请人： NOKIA TELECOMMUNICATIONS OY , OKSANEN, Toni , PATANA, Jari , VIITANEN, Esa , ALATALO, Hannu
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04L12/52
CPC分类号： H04J3/0623 , H04J2203/0089
摘要： The invention relates to a method for disassembling or assembling a frame structure used in a synchronous digital data communication system, such as the SDH or SONET system. In order to enable the disassembly or assembly of frame structures with less hardware than previously, and to allow a more efficient use of RAM memory blocks in such processes, the interpretation and generation process of the pointers of at least two signals on the same level of hierarchy is carried out at least at one processing stage on a time-division basis in a unit (61, 62) common to said signals.
摘要翻译：本发明涉及用于拆分或组装在诸如SDH或SONET系统的同步数字数据通信系统中使用的帧结构的方法。为了能够以比以前更少的硬件来拆卸或组装框架结构，并且为了在这样的过程中更有效地使用RAM存储器块，在相同级别上的至少两个信号的指针的解释和生成过程至少在时分的一个处理阶段，在所述信号共用的单元（61,62）中执行层次结构。

3. 发明申请

WO1994001946A1 METHOD FOR RECEIVING A SIGNAL USED IN A SYNCHRONOUS DIGITAL TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：用于接收同步数字电信系统中使用的信号的方法
公开(公告)号：WO1994001946A1
公开(公告)日：1994-01-20
申请号：PCT/FI1993000278
申请日：1993-07-01
申请人： NOKIA TELECOMMUNICATIONS OY , KIVI-MANNILA, Arvi , VIITANEN, Esa , PATANA, Jari , OKSANEN, Toni
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04J3/1611
摘要： The invention relates to a method for receiving a signal used in a synchronous digital telecommunication system. The method comprises pointer interpretation in which the receiver has three possible main states, between which it undergoes transitions under the control of event counters, the main states being a normal state (NORM), a loss of pointer state (LOP) and an alarm state (AIS), said counters counting predetermined events in each main state, said events comprising the reception of alarm data indicating an alarm (AIS-ind), the reception of a new data flag indicating a new pointer value (NDF-enable), the reception of the active pointer (active-point), and the reception of an invalid pointer (inv-point). In order for the fault tolerance of the system to be improved, all the pointers which do not indicate an alarm, a new data flag or the active pointer are considered invalid in the normal state (NORM).
摘要翻译：本发明涉及一种用于接收在同步数字电信系统中使用的信号的方法。该方法包括指针解释，其中接收机具有三个可能的主状态，它们在事件计数器的控制下经历转换，主状态是正常状态（NORM），指针状态丢失（LOP）和报警状态（AIS），所述计数器对每个主状态中的预定事件进行计数，所述事件包括接收到指示报警（AIS-ind）的报警数据，接收指示新指针值（NDF使能）的新数据标志，活动指针（活动点）的接收以及无效指针（inv-point）的接收。为了改善系统的容错性，在正常状态（NORM）中，不指示报警的所有指针，新数据标志或活动指针都被认为是无效的。

4. 发明申请

WO1995010897A1 A BUFFERING METHOD AND A BUFFER 审中-公开
标题翻译：缓冲方法和缓冲区
公开(公告)号：WO1995010897A1
公开(公告)日：1995-04-20
申请号：PCT/FI1994000462
申请日：1994-10-13
申请人： NOKIA TELECOMMUNICATIONS OY , OKSANEN, Toni , PATANA, Jari , VIITANEN, Esa
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： G06F5/16 , H04J3/0626
摘要： The present invention relates to a method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits. According to the method, data is written into the buffer memory in synchronism with a write clock signal (WR-CLK), and data is read from the buffer memory in synchronism with a read clock signal (RD-CLK). In order to implement the combined bit and byte buffer in the simplest possible manner, the buffer memory is composed of M pieces of one-bit data memory locations (14; 21), the figure M being selected so that the frame length F is divisible by the figure M and the figure M is divisible by the byte length, and that the synchronization data passed through the buffer is stored in a one-bit synchronization memory location (15; 24) adjacent to one data memory location (14; 21).
摘要翻译：本发明涉及一种在数字电信系统中执行缓冲的方法，其中数据以长度为F比特的帧传送。根据该方法，与写入时钟信号（WR-CLK）同步地将数据写入缓冲存储器，并且与读取时钟信号（RD-CLK）同步地从缓冲存储器读取数据。为了以最简单的方式实现组合的比特和字节缓冲器，缓冲存储器由M个一位数据存储器位置（14; 21）组成，所选择的图M使得帧长度F可以被整除通过图M和图M可以被字节长度整除，并且通过缓冲器传递的同步数据被存储在与一个数据存储器位置（14; 21）相邻的一位同步存储单元（15; 24）中，。

5. 发明申请

WO1994001947A1 METHOD FOR RECEIVING A SIGNAL USED IN A SYNCHRONOUS DIGITAL TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：用于接收同步数字电信系统中使用的信号的方法
公开(公告)号：WO1994001947A1
公开(公告)日：1994-01-20
申请号：PCT/FI1993000279
申请日：1993-07-01
申请人： NOKIA TELECOMMUNICATIONS OY , KIVI-MANNILA, Arvi , VIITANEN, Esa , PATANA, Jari , OKSANEN, Toni
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04J3/1611 , H04J3/07 , H04J2203/006
摘要： The invention relates to a method for receiving a signal used in a synchronous digital telecommunication system. The method comprises pointer interpretation in which the receiver has three possible main states (NORM, AIS, LOP), between which it undergoes transitions under the control of event counters. In order for fault tolerance to be improved and correction of error situations to be expedited, in the normal state (i) all the events in which the value "normal" (NDF-disabled) of the new data flag is received, and the majority of the I-bits is inverted, and the majority of the D-bits is not inverted are regarded as increment data, and (ii) all the events in which the value "normal" (NDF-disabled) of the new data flag is received, and the majority of the D-bits is inverted, and the majority of the I-bits is not inverted, are regarded as decrement data, wherein the value "normal" for the new data flag is considered to be "0110" and values differing therefrom within certain limits.
摘要翻译：本发明涉及一种用于接收在同步数字电信系统中使用的信号的方法。该方法包括指针解释，其中接收机具有三种可能的主状态（NORM，AIS，LOP），它们在事件计数器的控制下经历转换。为了提高容错性和加快错误情况的校正，在正常状态（i）接收到新数据标志的值“正常”（NDF禁用）的所有事件和大多数 I比特的大部分被反转，并且D比特的大多数不被反转，被认为是增量数据，并且（ii）新数据标志的值“正常”（NDF禁用）的所有事件是并且大多数D比特被反转，并且大多数I比特不被反相，被认为是减量数据，其中新数据标志的值“正常”被认为是“0110”，并且在某些限度内与其不同的值。

6. 发明申请

WO1993025031A1 METHOD AND EQUIPMENT FOR MONITORING THE FILL RATE OF AN ELASTIC BUFFER MEMORY IN A SYNCHRONOUS DIGITAL TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：用于监视同步数字电信系统中弹性缓冲存储器的填充速率的方法和设备
公开(公告)号：WO1993025031A1
公开(公告)日：1993-12-09
申请号：PCT/FI1993000238
申请日：1993-06-01
申请人： NOKIA TELECOMMUNICATIONS OY , OKSANEN, Toni , VIITANEN, Esa
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04L12/52
CPC分类号： H04Q11/0478 , G06F5/065 , H04J3/0623 , H04J2203/0019
摘要： The invention relates to a method and an equipment for monitoring the fill rate of an elastic buffer memory used in a synchronous digital telecommunication system, such as the SDH or SONET system. To enable the monitoring of the fill rate of the channels with less hardware than previously, the fill rate of at least two channels of the same level of hierarchy is monitored on a time-division basis in a monitoring unit (64) common to said channels.
摘要翻译：本发明涉及一种用于监视在诸如SDH或SONET系统的同步数字电信系统中使用的弹性缓冲存储器的填充率的方法和设备。为了能够以比以前更少的硬件来监视信道的填充率，在所述信道公共的监视单元（64）中以时分的方式监视同一级别的至少两个信道的填充速率。

7. 发明申请

WO1993025029A1 METHOD AND EQUIPMENT FOR ELASTIC BUFFERING IN A SYNCHRONOUS DIGITAL TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：用于同步数字电信系统中弹性缓冲的方法和设备
公开(公告)号：WO1993025029A1
公开(公告)日：1993-12-09
申请号：PCT/FI1993000236
申请日：1993-06-01
申请人： NOKIA TELECOMMUNICATIONS OY , OKSANEN, Toni , VIITANEN, Esa
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04L12/52
CPC分类号： H04J3/0623 , H04J2203/0012 , H04J2203/0089 , H04Q11/0478
摘要： The invention relates to a method and an equipment for elastic buffering in a synchronous digital telecommunication system, such as the SDH or SONET system. In order to allow elastic buffering with less hardware than previously and a more efficient use of RAM memory blocks than previously in the process, the elastic buffering of at least two signals of the same level of hierarchy is performed on a time-division basis in a buffer memory (101) common to said signals.
摘要翻译：本发明涉及一种同步数字电信系统（如SDH或SONET系统）中弹性缓冲的方法和设备。为了允许比以前更少的硬件进行弹性缓冲，并且比先前在该过程中更有效地使用RAM存储器块，对于等级层级的至少两个信号的弹性缓冲在时间分割的基础上执行对所述信号共用的缓冲存储器（101）。

8. 发明申请

WO1994003000A1 METHOD FOR RECEIVING A SIGNAL USED IN A SYNCHRONOUS DIGITAL TELECOMMUNICATION SYSTEM 审中-公开
标题翻译：用于接收同步数字电信系统中使用的信号的方法
公开(公告)号：WO1994003000A1
公开(公告)日：1994-02-03
申请号：PCT/FI1993000299
申请日：1993-07-15
申请人： NOKIA TELECOMMUNICATIONS OY , PATANA, Jari
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04J03/06
CPC分类号： H04J3/1611
摘要： The invention relates to a method for receiving a signal used in a synchronous digital telecommunication system, such as the SDH or SONET system. In order that frame synchronization could be found as quickly as possible after information about a change of the pointer value has been received e.g. as a result of transmission errors, a certain number of pointers following the change are checked, and the old pointer value is restored if at least half of said number of pointers following the change have the old pointer value. At least in the cases where exactly half of said number of pointers following the change have the old pointer value, the return is effected only if the number of new pointer values in said number of pointers is smaller than a certain predetermined number.
摘要翻译：本发明涉及用于接收在诸如SDH或SONET系统的同步数字电信系统中使用的信号的方法。为了在已经接收到关于指针值的改变的信息之后，可以尽可能快地找到帧同步。作为传输错误的结果，检查改变之后的一定数量的指针，并且如果改变后的所述指针数的至少一半具有旧指针值，则旧指针值被恢复。至少在更改后的所述指针数量的正好一半具有旧指针值的情况下，仅当所述指针数目中的新指针值的数量小于某个预定数量时才返回。

9. 发明申请

WO1995032599A2 NON-BLOCKING SWITCHING NETWORK 审中-公开
标题翻译：非阻塞开关网络
公开(公告)号：WO1995032599A2
公开(公告)日：1995-11-30
申请号：PCT/FI1995000288
申请日：1995-05-24
申请人： NOKIA TELECOMMUNICATIONS OY , AHOLA, Reijo , KASURINEN, Timo , KELLOCK, Hamish , SILLANPÄÄ, Tero , URALA, Reino , VIITANEN, Esa , WAINIO, Pekka
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H04Q11/06
CPC分类号： H04L49/1553 , H04J2203/0012 , H04J2203/0041 , H04L2012/561 , H04Q11/0478 , H04Q11/06 , H04Q2213/1334
摘要： The invention discloses a cross connect architecture for SDH signals, in which the input stage is composed of parallel TS switch blocks (TSW-SSW), the centre stage (MSW) is composed of parallel time and space switch blocks (STS; TxT-S) and the output stage is a symmetrical mirror image of the input stage. It is advantageous that the centre stage have a large number of blocks (MSW) relative to the minimum need, even double as many, whereby in practice a non-blocking switching network is obtained. All the switch blocks have doubled control memories, which ensure interference-free reconnections.
摘要翻译：本发明公开了一种用于SDH信号的交叉连接架构，其中输入级由并行TS交换块（TSW-SSW）组成，中心级（MSW）由并行时间和空间交换块（STS; TxT-S ），输出级是输入级的对称镜像。有利的是，中心级具有相对于最小需求的大量块（MSW），甚至是双倍数，从而在实践中获得非阻塞交换网络。所有的开关块都具有双倍的控制存储器，确保无干扰的重新连接。

10. 发明申请

WO1994008398A1 LINE DRIVER CIRCUIT 审中-公开
标题翻译：线路驱动电路
公开(公告)号：WO1994008398A1
公开(公告)日：1994-04-14
申请号：PCT/FI1993000400
申请日：1993-10-06
申请人： NOKIA TELECOMMUNICATIONS OY , HENRIKSSON, Markku , KATZ, Marcos , RISTIMÄKI, Hemmo , SAHLMAN, Kari
发明人： NOKIA TELECOMMUNICATIONS OY
IPC分类号： H03K17/16
CPC分类号： H04L25/0266 , H04B3/04
摘要： The invention relates to a line driver circuit, comprising a driver stage (11) and a transformer provided with a primary and secondary windings (12a, 12b) in such a way that output terminals of the driver stage (11) are connected to terminals of the primary winding (12a) of the transformer and terminals of the secondary winding (12b) of the transformer are connected to a transmission line (13), at least one matching resistor (Rm) being connected to the terminals of the primary winding of the line driver circuit. To provide a line driver circuit having a good return loss and a low power consumption, it comprises driver means (51 to 53; 71, 72; 81, Q1, Q2) connected to said at least one matching resistor and responsive to an output signal of the driver stage (11) for disconnecting the matching resistor (Rm; Rm1, Rm2) for the time of pulses transmitted by the driver stage.
摘要翻译：本发明涉及一种线路驱动电路，其包括驱动器级（11）和设置有初级和次级绕组（12a，12b）的变压器，使得驱动器级（11）的输出端子连接到变压器的初级绕组（12a）和变压器的次级绕组（12b）的端子连接到传输线（13），至少一个匹配电阻器（Rm）连接到第一绕组线路驱动电路。为了提供具有良好的回波损耗和低功耗的线路驱动器电路，它包括连接到所述至少一个匹配电阻器并且响应于输出信号的驱动器装置（51至53; 71,72; 81，Q1，Q2）用于在驱动器级发送的脉冲时间中断开匹配电阻器（Rm; Rm1，Rm2）的驱动器级（11）。

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